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2020 – today
- 2024
[j19]Chi-Chou Kao, Hung-Yi Lin:
Performance-Oriented Layout Synthesis for Quantum Computing. Comput. Syst. Sci. Eng. 48(6): 1581-1594 (2024)- 2023
- [j18]Chi-Chou Kao
:
Optimizing FPGA-Based Convolutional Neural Network Performance. J. Circuits Syst. Comput. 32(15): 2350254:1-2350254:19 (2023) - [j17]Chi-Chou Kao:
Performance-oriented FPGA-based convolution neural network designs. Multim. Tools Appl. 82(14): 21019-21030 (2023) - 2020
- [j16]Chi-Chou Kao:
Resource and Performance Tradeoff for Task Scheduling of Parallel Reconfigurable Architectures. J. Circuits Syst. Comput. 29(2): 2050029:1-2050029:14 (2020) - [j15]Chi-Chou Kao:
Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding. Multim. Tools Appl. 79(41-42): 30583-30599 (2020)
2010 – 2019
- 2019
- [j14]Chi-Chou Kao:
Design and Implementation of Stereoscopic Image Generation. J. Circuits Syst. Comput. 28(8): 1950133:1-1950133:21 (2019) - 2017
- [j13]Chi-Chou Kao:
Stereoscopic image generation with depth image based rendering. Multim. Tools Appl. 76(11): 12981-12999 (2017) - [j12]Chi-Chou Kao, Yi-Ciang Lin:
Designs of Low Power Snoop for Multiprocessor System on Chip. J. Signal Process. Syst. 88(1): 83-89 (2017) - 2015
- [j11]Chi-Chou Kao:
Performance-Oriented Partitioning for Task Scheduling of Parallel Reconfigurable Architectures. IEEE Trans. Parallel Distributed Syst. 26(3): 858-867 (2015) - [j10]Chi-Chou Kao:
Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction. J. Signal Process. Syst. 79(1): 99-104 (2015) - 2013
- [j9]Chi-Chou Kao, Yen-Tai Lai:
Improved Time-Multiplexed FPGA Architecture and Algorithm for Minimizing Communication Cost Designs. J. Circuits Syst. Comput. 22(5) (2013) - [c7]Chi-Chou Kao:
E-Health Design of EEG Signal Classification for Epilepsy Diagnosis. ISBAST 2013: 67-71 - 2012
- [c6]Chi-Chou Kao, Yen-Tai Lai, Chao-Feng Tseng:
Laplacian-based H.264 intra-prediction mode decision. CHINACOM 2012: 638-641 - 2011
- [j8]Chi-Chou Kao:
BDD-based synthesis for mixed CMOS/PTL logic. Int. J. Circuit Theory Appl. 39(9): 923-932 (2011) - [j7]Wen-Lin Yang, Chi-Chou Kao, Cheng-Huang Tung:
Heuristic Algorithms for Constructing Interference-Free and Delay-Constrained Multicast Trees for Wireless Mesh Networks. KSII Trans. Internet Inf. Syst. 5(2): 269-286 (2011) - 2010
- [j6]Chi-Chou Kao, Yen-Tai Lai, Chia-Hui Lin:
An efficient reflection invariance region-based image retrieval framework. Int. J. Imaging Syst. Technol. 20(2): 155-161 (2010) - [j5]Yen-Tai Lai, Chi-Chou Kao, Tzu-Chiang Tai, Wen-Chun Yeh:
A Performance-Driven Rotational Invariant Image Retrieval System. J. Inf. Sci. Eng. 26(6): 2009-2022 (2010)
2000 – 2009
- 2009
- [c5]Yen-Tai Lai, Chia-Nan Yeh, Chi-Chou Kao:
A Novel Digital Pixel Sensor System. ISCAS 2009: 2297-2300 - 2008
- [j4]Chi-Chou Kao:
Computer-aided crosstalk minimisation design for system-on-chip. IET Comput. Digit. Tech. 2(1): 23-29 (2008) - 2007
- [j3]Chi-Chou Kao:
A High Flexibility Design for Clock Distribution Network in System on Chip. J. Circuits Syst. Comput. 16(1): 51-63 (2007) - 2005
- [j2]Chi-Chou Kao, Yen-Tai Lai:
An efficient algorithm for finding the minimal-area FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 10(1): 168-186 (2005) - 2004
- [c4]Chi-Chou Kao, Yen-Tai Lai:
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction. ASP-DAC 2004: 719-724 - 2003
- [j1]Chi-Chou Kao:
Design of echo cancellation and noise elimination for speech enhancement. IEEE Trans. Consumer Electron. 49(4): 1468-1473 (2003) - [c3]Chi-Chou Kao, Yen-Tai Lai:
A technology mapping algorithm for heterogeneous FPGAs. ASP-DAC 2003: 213-216
1990 – 1999
- 1999
- [c2]Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh:
A quadratic programming method for interconnection crosstalk minimization. ISCAS (6) 1999: 270-273 - [c1]Chi-Chou Kao, Yen-Tai Lai:
A routability and performance driven technology mapping algorithm for LUT based FPGA designs. ISCAS (1) 1999: 474-477
Coauthor Index
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