"VLSI architecture and chip for combined invisible robust and fragile ..."

Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan (2007)

> Home

Details and statistics

DOI: 10.1049/IET-CDT:20070057

access: closed

type: Journal Article

metadata version: 2020-07-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/iet-cdt/MohantyKR07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/iet-cdt/MohantyKR07
Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan:
VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Comput. Digit. Tech. 1(5): 600-611 (2007)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.