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ORCIDASAP 2002: San Jose, CA, USA
- 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA. IEEE Computer Society 2002, ISBN 0-7695-1712-9
Keynote Presentation
- José A. B. Fortes:
Nanocomputing with Delays. 3-
Design Methodologies
- Manju Manjunathaiah, Graham M. Megson:
Compositional Technique for Synthesising Multi-Phase Regular Arrays. 7-16 - Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks. 17-28 - Holger Blume
, H. Hübert, H. T. Feldkämper, Tobias G. Noll:
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. 29-40 - Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima:
A Component Architecture for FPGA-Based, DSP System Design. 41-
Low Power Design
- Wen-Tsong Shiue:
Low Power Memory Design. 55-64 - Mark G. Arnold:
Reduced Power Consumption for MPEG Decoding with LNS. 65-75 - Sumit Mohanty, Seonil Choi, Ju-wook Jang, Viktor K. Prasanna:
A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs. 76-87 - Lin Yuan, Gang Qu:
Design Space Exploration for Energy-Efficient Secure Sensor Network. 88-
Computer Arithmetic I
- José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Logarithm with Selection by Rounding. 101-110 - Chang Yong Kang, Earl E. Swartzlander Jr.:
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. 111-119 - David W. Matula, Alex Fit-Florea, Lee D. McFearin:
Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup. 120-129 - Roberto Muscedere, Vassil S. Dimitrov, Graham A. Jullien, William C. Miller:
Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up Tables. 130-
Memory Organization
- James Irwin, David May, Henk L. Muller, Dan Page:
Predictable Instruction Caching for Media Processors. 141-150 - Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen:
A Mathematical Model of Trace Cache. 151-162 - Jeffrey T. Draper, Jeff Sondeen, Sumit D. Mediratta, Ihn Kim:
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. 163-172 - Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, Sung-Bong Yang:
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. 173-
Computer Arithmetic II
- Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli:
Fast Radix-4 Retimed Division with Selection by Comparisons. 185-196 - Neil Burgess:
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications. 197-207 - Ahmet Akkas:
A Combined Interval and Floating-Point Comparator/Selector. 208-217 - Peter Kornerup:
Reviewing 4-to-2 Adders for Multi-Operand Addition. 218-
Media Processors
- Byeong Kil Lee, Lizy Kurian John:
Implications of Programmable General Purpose Processors for Compression/Encryption Applications. 233-242 - Chris Y. Chung, Ravi Managuli, Yongmin Kim:
Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline. 243-252 - Ruby B. Lee, A. Murat Fiskiran, Zhijie Shi, Xiao Yang:
Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments. 253-264 - Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata:
Polynomial Evaluation on Multimedia Processors. 265-
Cryptography
- Chih-Chung Lu, Shau-Yin Tseng:
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter. 277-285 - James Irwin, Dan Page, Nigel P. Smart:
Instruction Stream Mutation for Non-Deterministic Processors. 286-295 - Mehboob Alam, Wael M. Badawy, Graham A. Jullien:
A Novel Pipelined Threads Architecture for AES Encryption Algorithm. 296-302 - Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri:
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard. 303-
VLSI Architectures
- E. I. Chester, John N. Coleman:
Matrix Engine for Signal Processing Applications Using the Logarithmic Number System. 315-324 - K. Sitaraman, N. Ranganathan, Abdel Ejnioui:
A VLSI Architecture for Object Recognition Using Tree Matching. 325-334 - Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. 335-343 - Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy:
Optical Network Reconfiguration for Signal Processing Applications. 344-
Application-Specific System Design
- Alain Darte, Guillaume Huard:
New Results on Array Contraction. 359-370 - Tsai-Yun Liao, Ta-Yin Hu:
A CORBA-Based GIS-T for Ambulance Assignment. 371-380 - David Cachera, Tanguy Risset:
Advances in Bit Width Selection Methodology. 381-390 - Michael D. DeVore, Roger D. Chamberlain, George Engel, Joseph A. O'Sullivan, Mark A. Franklin:
Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System. 391-
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