default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDTobias G. Noll
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2010 – 2019
- 2018
[c78]Arne Heittmann, Tobias G. Noll:
Architecture and optimization of associative memories used for the implementation of logic functions based on nanoelectronic 1S1R cells. DATE 2018: 1496-1499- 2017
- [j24]Georgia Psychou
, Dimitrios Rodopoulos, Mohamed M. Sabry, Tobias Gemmeke, David Atienza, Tobias G. Noll, Francky Catthoor:
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems. ACM Comput. Surv. 50(4): 50:1-50:38 (2017) - [j23]Michael Meixner, Tobias G. Noll:
Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 787-791 (2017) - [j22]Martin Broich, Tobias G. Noll:
Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency. J. Signal Process. Syst. 87(3): 299-325 (2017) - [c77]Arne Heittmann, Tobias G. Noll:
Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells. NANOARCH 2017: 119-124 - 2016
- [j21]Upasna Vishnoi, Michael Meixner, Tobias G. Noll:
A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency. J. Signal Process. Syst. 83(3): 329-356 (2016) - [c76]Georgia Psychou, Tobias Gemmeke, Tobias G. Noll:
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects. PATMOS 2016: 147-154 - 2015
- [j20]Dimitrios Rodopoulos, Georgia Psychou, Mohamed M. Sabry, Francky Catthoor, Antonis Papanikolaou, Dimitrios Soudris, Tobias G. Noll, David Atienza:
Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations. ACM Comput. Surv. 47(3): 38:1-38:33 (2015) - [c75]Georgia Psychou, Tobias Gemmeke, Tobias G. Noll:
On the use of analytical techniques for reliability analysis in presence of hardware-induced errors. INDIN 2015: 1416-1423 - [c74]Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig 2015: 1-8 - 2014
- [c73]Arne Heittmann, Tobias G. Noll:
Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit. ISCAS 2014: 1656-1659 - [c72]Martin Broich, Tobias G. Noll:
Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders. ISSoC 2014: 1-8 - [c71]Michael Meixner, Tobias G. Noll:
Limits of gate-level power estimation considering real delay effects and glitches. ISSoC 2014: 1-7 - [c70]Michael Meixner, Tobias G. Noll:
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption. VLSID 2014: 415-420 - 2013
- [c69]Arne Heittmann, Tobias G. Noll:
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation. ASP-DAC 2013: 503-508 - [c68]Xiaolin Chen, Shuai Li, Jochen Schleifer, Thomas Coenen, Anupam Chattopadhyay, Gerd Ascheid, Tobias G. Noll:
High-level modeling and synthesis for embedded FPGAs. DATE 2013: 1565-1570 - [c67]Upasna Vishnoi, Tobias G. Noll:
Cross-layer optimization of QRD accelerators. ESSCIRC 2013: 263-266 - [c66]Arne Heittmann, Tobias G. Noll:
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits. ACM Great Lakes Symposium on VLSI 2013: 137-142 - [c65]Qin Wang, Arne Heittmann, Tobias G. Noll:
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays. ACM Great Lakes Symposium on VLSI 2013: 233-238 - [c64]Upasna Vishnoi, Tobias G. Noll:
A family of modular area- and energy-efficient QRD-accelerator architectures. ISSoC 2013: 1-8 - [c63]Yuan Ren, Tobias G. Noll:
Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Based on Accurate Cost Models. VLSI-SoC (Selected Papers) 2013: 69-93 - [c62]Yuan Ren, Tobias G. Noll:
An accurate power estimation model for low-power hierarchical-architecture SRAMs. VLSI-SoC 2013: 144-149 - 2012
- [c61]Arne Heittmann, Tobias G. Noll:
A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights. ESANN 2012 - [c60]Arne Heittmann, Tobias G. Noll:
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. ACM Great Lakes Symposium on VLSI 2012: 227-232 - [c59]Martin Broich, Tobias G. Noll:
Efficient VLSI architectures of QPP interleavers for LTE turbo decoders. ISSoC 2012: 1-6 - [c58]Arne Heittmann, Tobias G. Noll:
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars. NANOARCH 2012: 93-100 - [c57]Tobias Gemmeke, Maryam Ashouei, Tobias G. Noll:
Noise Margin Based Library Optimization Considering Variability in Sub-threshold. PATMOS 2012: 72-82 - [c56]Matthias Korb, Tobias G. Noll:
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations. ICSAMOS 2012: 294-301 - [c55]Yuan Ren, Michael Gansen, Tobias G. Noll:
Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme. SoCC 2012: 224-229 - [c54]Upasna Vishnoi, Michael Meixner, Tobias G. Noll:
An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks. SoCC 2012: 242-247 - 2011
- [j19]Jochen Schleifer, Thomas Coenen, Tobias G. Noll:
Statistical modeling of reliability in logic devices. Microelectron. Reliab. 51(9-11): 1469-1473 (2011) - [c53]Matthias Korb, Tobias G. Noll:
Area- and energy-efficient high-throughput LDPC decoders with low block latency. ESSCIRC 2011: 75-78 - [c52]Arne Heittmann, Tobias G. Noll:
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization. ACM Great Lakes Symposium on VLSI 2011: 375-378 - 2010
- [j18]Alexander Behrens, Linus Atorf, Robert Schwann, Bernd Neumann, Rainer Schnitzler, Johannes Ballé, Thomas Herold, Aulis Telle, Tobias G. Noll, Kay Hameyer, Til Aach:
MATLAB Meets LEGO Mindstorms - A Freshman Introduction Course Into Practical Engineering. IEEE Trans. Educ. 53(2): 306-317 (2010) - [j17]Götz Kappen, Lothor Kurz, O. Priebe, Tobias G. Noll:
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers. J. Signal Process. Syst. 58(1): 41-51 (2010) - [c51]Emrah Tasdemir, Götz Kappen, Tobias G. Noll:
Potential of using block floating point arithmetic in ASIP-based GNSS-receivers. ASAP 2010: 293-296 - [c50]Ingo Rust, Tobias G. Noll:
A radix-4 single-precision floating point divider based on digit set interleaving. ISCAS 2010: 709-712 - [c49]Thomas Coenen, Jochen Schleifer, Oliver Weiß, Tobias G. Noll:
Interconnect routing of embedded FPGAs using standard VLSI routing tools. SoC 2010: 121-124 - [c48]Ingo Rust, Tobias G. Noll:
A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point. SoC 2010: 150-153 - [c47]Matthias Korb, Tobias G. Noll:
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates. SoC 2010: 169-172 - [p1]Tobias G. Noll, Thorsten von Sydow, Bernd Neumann, Jochen Schleifer, Thomas Coenen, Götz Kappen:
Reconfigurable Components for Application-Specific Processor Architectures. Dynamically Reconfigurable Systems 2010: 25-49
2000 – 2009
- 2009
- [c46]Matthias Korb, Tobias G. Noll:
Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures. ESSCIRC 2009: 408-411 - 2008
- [j16]Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek:
OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis. J. Syst. Archit. 54(11): 1019-1029 (2008) - [j15]Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll:
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 781-791 (2008) - [j14]Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll:
Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs. J. Signal Process. Syst. 53(1-2): 129-143 (2008) - [c45]Bernd Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll:
Design flow for embedded FPGAs based on a flexible architecture template. DATE 2008: 56-61 - [c44]Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll:
Application-specific reconfigurable processors. FPL 2008: 350 - [c43]Gerhard Tech, Robert Schwann, Götz Kappen, Michael Först, Tobias G. Noll:
Adaptive kernel algorithm for FPGA-based speckle reduction. Medical Imaging: Image Processing 2008: 691424 - [c42]Jörg von Livonius, Holger Blume, Tobias G. Noll:
Design of a Pareto-optimization environment and its application to motion estimation. MMSP 2008: 838-843 - [c41]Thorsten von Sydow, Holger Blume, Götz Kappen, Tobias G. Noll:
ASIP-eFPGA Architecture for Multioperable GNSS Receivers. SAMOS 2008: 136-145 - 2007
- [j13]Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll:
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures. J. Syst. Archit. 53(8): 466-476 (2007) - [j12]Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll:
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. J. Syst. Archit. 53(10): 689-702 (2007) - [c40]Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll:
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. ASAP 2007: 296-301 - [c39]Alexander Flocke, Tobias G. Noll:
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory. ESSCIRC 2007: 328-331 - [c38]Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll:
A Power Estimation Model for an FPGA-based Softcore Processor. FPL 2007: 171-176 - [c37]Martin Botteck, Holger Blume, Jörg von Livonius, Martin Neuenhahn, Tobias G. Noll:
Programmable Architectures for Realtime Music Decompression. PARCO 2007: 777-784 - [c36]Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek:
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. ICSAMOS 2007: 74-81 - 2006
- [j11]Holger Blume, Thorsten von Sydow, Tobias G. Noll:
A Case Study for the Application of Deterministic and Stochastic Petri Nets in the SoC Communication Domain. J. VLSI Signal Process. 43(2-3): 223-233 (2006) - [c35]Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny:
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW 2006: 56 - [c34]Thorsten von Sydow, Bernd Neumann, Holger Blume, Tobias G. Noll:
Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic. ASAP 2006: 125-131 - [c33]Götz Kappen, Tobias G. Noll:
Application specific instruction processor based implementation of a GNSS receiver on an FPGA. DATE Designers' Forum 2006: 58-63 - [c32]Tobias G. Noll, Uwe Lambrette:
Cross disciplinary aspects (4G wireless special day). DATE 2006: 726 - [c31]Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny:
Design and analysis of matching circuit architectures for a closest match lookup. IPDPS 2006 - [c30]Thorsten von Sydow, Matthias Korb, Bernd Neumann, Holger Blume, Tobias G. Noll:
Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros. ReConFig 2006: 252-261 - [c29]Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll:
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. SAMOS 2006: 216-226 - [c28]Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll:
A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. SoCC 2006: 271-274 - 2005
- [j10]Holger Blume, H. T. Feldkämper, Tobias G. Noll:
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. J. VLSI Signal Process. 40(1): 19-34 (2005) - [c27]Gordian Prescher, Tobias Gemmeke, Tobias G. Noll:
A parametrizable low-power high-throughput turbo-decoder. ICASSP (5) 2005: 25-28 - [c26]José L. Rodríguez-Navarro, Michael Gansen, Tobias G. Noll:
Error-tolerant FIR filters based on low-cost residue codes. ISCAS (5) 2005: 5210-5213 - [c25]Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll:
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets. SAMOS 2005: 374-383 - 2004
- [j9]Tobias Gemmeke, Michael Gansen, Heinrich J. Stockmanns, Tobias G. Noll:
Design optimization of low-power high-performance DSP building blocks. IEEE J. Solid State Circuits 39(7): 1131-1139 (2004) - [c24]Tobias Gemmeke, Tobias G. Noll:
A physically oriented model to quantify the dynamic noise margin [on-chip noise]. ESSCIRC 2004: 467-470 - [c23]Tobias Gemmeke, Tobias G. Noll:
A Physically Oriented Model to Quantify the Noise-on-Delay Effect. PATMOS 2004: 879-888 - [c22]Holger Blume, Thorsten von Sydow, Tobias G. Noll:
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets. SAMOS 2004: 484-493 - [c21]Holger Blume, Jörg von Livonius, Tobias G. Noll:
Segmentation in the loop: an iterative object-based algorithm for motion estimation. VCIP 2004 - 2002
- [j8]Tobias Gemmeke, Michael Gansen, Tobias G. Noll:
Implementation of scalable power and area efficient high-throughput Viterbi decoders. IEEE J. Solid State Circuits 37(7): 941-948 (2002) - [j7]Holger Blume, G. Herczeg, O. Erdler, Tobias G. Noll:
Object based refinement of motion vector fields applying probabilistic homogenization rules. IEEE Trans. Consumer Electron. 48(3): 694-701 (2002) - [j6]Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll:
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. J. VLSI Signal Process. 31(2): 117-126 (2002) - [c20]Holger Blume, H. Hübert, H. T. Feldkämper, Tobias G. Noll:
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. ASAP 2002: 29-40 - 2000
- [c19]V. S. Gierenz, Oliver Weiss, Tobias G. Noll, I. Carew, Jonathan J. Ashley, Razmik Karabed:
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder. ASAP 2000: 195- - [c18]Hans-Martin Blüthgen, Tobias G. Noll:
A Programmable Processor for Approximate String Matching with High Throughput Rate. ASAP 2000: 309- - [c17]Hans-Martin Blüthgen, Patrick Osterloh, Holger Blume, Tobias G. Noll:
A Hardware Implementation for Approximate Text Search in Multimedia Applications. IEEE International Conference on Multimedia and Expo (III) 2000: 1425-1428
1990 – 1999
- 1998
- [j5]Christian Lütkemeyer, Tobias G. Noll:
A transversal equalizer with an increased adaptation speed and tracking capability. IEEE J. Solid State Circuits 33(3): 503-507 (1998) - [j4]Arndt Glowinski, Jürgen Küsch, Gerhard Adam, Arno Bücker, Tobias G. Noll, Rolf W. Günther:
Device visualization for interventional MRI using local magnetic fields: Basic theory and its application to catheter visualization. IEEE Trans. Medical Imaging 17(5): 794-802 (1998) - [j3]Jan Peter Berns, Tobias G. Noll:
A Flexible 200 GOPS HDTV Motion Estimation Chip. J. VLSI Signal Process. 19(2): 85-95 (1998) - [c16]K. Eck, Andreas R. Brenner, Wolfgang Wilhelm, Tobias G. Noll:
Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung. Bildverarbeitung für die Medizin 1998 - [c15]Robert Schwann, K. Eck, Andreas R. Brenner, Tobias G. Noll:
Tiefenangepaßte Filterung für das Puls-Echo-Verfahren in der Ultraschalldiagnostik. Bildverarbeitung für die Medizin 1998 - [c14]Wolfgang Wilhelm, A. Kaufmann, Tobias G. Noll:
A new scalable VLSI architecture for Reed-Solomon decoders. CICC 1998: 13-16 - [c13]Christiane Henning, Tobias G. Noll:
Architecture and implementation of a bitserial sorter for weighted median filtering. CICC 1998: 189-192 - [c12]Christian Lütkemeyer, Hans-Martin Blüthgen, Tobias G. Noll:
A hybrid equalizer merging the advantages of Baud spaced and fractionally spaced equalizers. ICASSP 1998: 3357-3360 - 1997
- [c11]Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll:
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. ASAP 1997: 438-447 - [c10]Wolfgang Wilhelm, Tobias G. Noll:
A novel systematic mapping approach for highly efficient multiplexed FIR-filter architectures. ICASSP 1997: 651-654 - 1996
- [c9]Jan Peter Berns, Tobias G. Noll:
A Flexible Motion Estimation Chip for Variable Size Block Matching. ASAP 1996: 112-121 - [c8]K. Eck, Andreas R. Brenner, Tobias G. Noll:
Korrektur der Phasenaberration in Ultraschallaufnahmen durch das Dynamic-Time-Warping Verfahren. Bildverarbeitung für die Medizin 1996 - [c7]S. Kannengießer, Andreas R. Brenner, Tobias G. Noll:
Artefaktreduzierung in der ultraschnellen Magnetresonanz-Bildgebung mittels inverser Filterung im Ortsfrequenzbereich. Bildverarbeitung für die Medizin 1996 - 1995
- [j2]Erik De Man, Michael Schulz, Richard Schmidmaier, Matthias Schöbinger, Tobias G. Noll:
Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications. IEEE J. Solid State Circuits 30(3): 219-227 (1995) - 1994
- [c6]Matthias Schöbinger, Tobias G. Noll:
Low Power CMOS Design Strategies. DAC 1994: 594-595 - [c5]Erik De Man, Matthias Schöbinger, Tobias G. Noll, Georg Sebald:
A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM Demodulators. ISCAS 1994: 275-278 - 1991
- [j1]Tobias G. Noll:
Carry-save architectures for high-speed digital signal processing. J. VLSI Signal Process. 3(1-2): 121-140 (1991) - 1990
- [c4]U. Totzek, F. Matthiesen, S. Wohlleben, Tobias G. Noll:
CMOS VLSI implementation of the 2D-DCT with linear processor arrays. ICASSP 1990: 937-940
1980 – 1989
- 1989
- [c3]Luc de Vos, M. Stegherr, Tobias G. Noll:
VLSI architectures for the full-search blockmatching algorithm. ICASSP 1989: 1687-1690 - 1984
- [c2]Robert Kavaler, Robert W. Brodersen, Tobias G. Noll, Menahem Lowy, Hy Murveit:
A dynamic time warp IC for a one thousand word recognition system. ICASSP 1984: 375-378 - [c1]Walter Ulbrich, Tobias G. Noll, B. Zehner:
MOS-VLSI pipelined digital filters for video applications. ICASSP 1984: 386-389
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 23:12 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
