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ORCIDThe Journal of VLSI Signal Processing, Volume 31
Volume 31, Number 1, May 2002
- Yu Hen Hu, Jan Larsen:
Guest Editorial. 5 - Joaquín Míguez, Luis Castedo
:
Maximum Likelihood Unsupervised Source Separation in Gaussian Noise. 7-18 - Marc M. Van Hulle:
Blind Source Separation and Equiprobabilistic Topographic Maps. 19-30 - Dongxiang Xu, Jenq-Neng Hwang, Chun Yuan:
Segmentation of Multi-Channel Image with Markov Random Field Based Active Contour Model. 45-55 - Karim Abed-Meraim, Ammar Chkeif, Yingbo Hua, Samir Attallah:
On a Class of Orthonormal Algorithms for Principal and Minor Subspace Tracking. 57-70
Volume 31, Number 2, June 2002
- Michael J. Schulte, Graham A. Jullien:
Guest Editorial. 75-76 - Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. 77-89 - H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller:
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming. 91-100 - William L. Freking, Keshab K. Parhi:
Performance-Scalable Array Architectures for Modular Multiplication. 101-116 - Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll:
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality. 117-126 - Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. 127-142 - Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang:
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. 143-156 - Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. 157-171 - Wael M. Badawy, Magdy A. Bayoumi:
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation. 173-184
Volume 31, Number 3, July 2002
- Luca Breveglieri, Vincenzo Piuri:
Digital Median Filters. 191-206 - Ramaswamy Govindarajan, Guang R. Gao, Palash Desai:
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. 207-229 - A. Benjamin Premkumar, A. S. Madhukumar:
An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform. 231-241 - Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu:
Synthesis and Optimization of Combinational Interface Circuits. 243-261 - Neil Burgess:
The Flagged Prefix Adder and its Applications in Integer Arithmetic. 263-271
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