default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDPeter Pirsch
Person information
- affiliation: University of Hanover, Germany
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2020
[j31]Mario Garrido
, Peter Pirsch:
Continuous-Flow Matrix Transposition Using Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3035-3046 (2020)
2010 – 2019
- 2017
- [c84]M. Wielage, Fabian Cholewa, Christian Fahnemann, Peter Pirsch, Holger Blume:
High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. CANDAR 2017: 351-357 - 2016
- [c83]Fabian Cholewa, M. Wielage, Peter Pirsch, Holger Blume:
An FPGA architecture for velocity independent backprojection in FMCW-based SAR systems. ISSPIT 2016: 252-257 - 2013
- [j30]Stefan Langemeyer, Peter Pirsch, Holger Blume:
Using SDRAM Memories for High-Performance Accesses to Two-Dimensional Matrices Without Transpose. Int. J. Parallel Program. 41(2): 331-354 (2013) - [p1]Christian Banz, Holger Blume, Peter Pirsch:
Architectures for Stereo Vision. Handbook of Signal Processing Systems 2013: 483-515 - 2011
- [c82]Stefan Langemeyer, Peter Pirsch, Holger Blume:
A FPGA architecture for real-time processing of variable-length FFTS. ICASSP 2011: 1705-1708 - [c81]Christian Banz, Holger Blume, Peter Pirsch:
Real-time semi-global matching disparity estimation on the GPU. ICCV Workshops 2011: 514-521 - [c80]Stefan Langemeyer, Peter Pirsch, Holger Blume:
Using SDRAMs for two-dimensional accesses of long 2n × 2m-point FFTs and transposing. ICSAMOS 2011: 242-248 - 2010
- [j29]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
A Multi-Shared Register File Structure for VLIW Processors. J. Signal Process. Syst. 58(2): 215-231 (2010) - [c79]Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch:
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ASAP 2010: 151-158 - [c78]Holger Flatt, Holger Blume, Peter Pirsch:
Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution. ReConFig 2010: 452-457 - [c77]Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer:
A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing. ICSAMOS 2010: 45-54 - [c76]Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch:
Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation. ICSAMOS 2010: 93-101
2000 – 2009
- 2009
- [c75]Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch:
An Enhanced DMA Controller in SIMD Processors for Video Applications. ARCS 2009: 159-170 - [c74]Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch:
Instruction merging to increase parallelism in VLIW architectures. SoC 2009: 143-146 - [c73]Holger Flatt, Ingo Schmädecke, Michael Kärgel, Holger Blume, Peter Pirsch:
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures. ICSAMOS 2009: 125-132 - [c72]Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch:
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams. SoCC 2009: 427-431 - 2008
- [c71]Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, Peter Pirsch:
A parallel hardware architecture for connected component labeling based on fast label merging. ASAP 2008: 144-149 - [c70]Konstantin Septinus, Christian Grimm, Vladislav Rumyantsev, Peter Pirsch:
On the Benefit of Caching Traffic Flow Data in the Link Buffer. SAMOS 2008: 2-11 - 2007
- [c69]Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch:
Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ARCS 2007: 254-267 - [c68]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. DSD 2007: 215-221 - [c67]Konstantin Septinus, Thuyen Le, Ulrich Mayer, Peter Pirsch:
On the Design of Scalable Massively Parallel CRC Circuits. ICECS 2007: 142-145 - [c66]Norman Nolte, Winfried Gehrke, Frank Wiczinowski, Peter Pirsch:
Scalable Multi-Standard LSI Texture Encoder for MPEG and VC-1 Video Compression. ICME 2007: 1187-1190 - [c65]Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch:
Design Space Exploration of Media Processors: A Parameterized Scheduler. ICSAMOS 2007: 41-49 - [c64]Holger Flatt, Sebastian Hesselbarth, Sebastian Flügel, Peter Pirsch:
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing. SAMOS 2007: 241-250 - [c63]Guillermo Payá Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch:
ChipDesign: from theory to real world. WCAE 2007: 58-64 - 2006
- [c62]Sebastian Flügel, Heiko Klußmann, Peter Pirsch, Marco Schulz, Malik Cisse, Winfried Gehrke:
A Highly Parallel Sub-Pel Accurate Motion Estimator for H.264. MMSP 2006: 387-390 - 2005
- [j28]Hans-Joachim Stolberg, Mladen Berekovic, Sören Moch, Lars Friebe, Mark Bernd Kulaczewski, Sebastian Flügel, Heiko Klußmann, Andreas Dehnhardt, Peter Pirsch:
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing. J. VLSI Signal Process. 41(1): 9-20 (2005) - [j27]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch:
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. J. VLSI Signal Process. 41(2): 139-151 (2005) - [c61]Matthias Winter, Peter Pirsch:
Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration. GI Jahrestagung (1) 2005: 458 - [c60]Andreas Dehnhardt, Mark Bernd Kulaczewski, Lars Friebe, Sören Moch, Peter Pirsch, Hans-Joachim Stolberg, Carsten Reuter:
A multi-core SoC design for advanced image and video compression. ICASSP (5) 2005: 665-668 - [c59]Stefan Langemeyer, Christian Simon-Klar, Norman Nolte, Peter Pirsch:
Architecture of a flexible on-board real-time SAR-processor. IGARSS 2005: 1746-1749 - [c58]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. SAMOS 2005: 32-40 - 2004
- [j26]Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, Andreas Dehnhardt, Peter Pirsch:
HIBRID-SOC: a multi-core architecture for image and video applications. SIGARCH Comput. Archit. News 32(3): 55-61 (2004) - [j25]Mladen Berekovic, Sören Moch, Peter Pirsch:
A scalable, clustered SMT processor for digital signal processing. SIGARCH Comput. Archit. News 32(3): 62-69 (2004) - [c57]Norman Nolte, Christian Simon-Klar, Stefan Langemeyer, Martin Kirscht, Peter Pirsch:
Next generation on-board SAR processor for compact airborne systems. IGARSS 2004: 1514-1517 - [c56]Carsten Reuter, Javier Martín-Langerwerf, Hans-Joachim Stolberg, Peter Pirsch:
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms. SAMOS 2004: 69-77 - 2003
- [c55]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Xun Mao, Mark Bernd Kulaczewski, Heiko Klußmann, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications. DATE 2003: 20008-20013 - [c54]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Sebastian Flügel, Mark Bernd Kulaczewski, Peter Pirsch:
HiBRID-SoC: a multi-core architecture for image and video applications. ICIP (3) 2003: 101-104 - [c53]Jörn Jachalsky, Martin Wahler, Peter Pirsch, S. Capperon, Winfried Gehrke, W. M. Kruijtzer, Antonio Núñez:
A core for ambient and mobile intelligent imaging applications. ICME 2003: 1-4 - [c52]Stefan Langemeyer, Helge Kloos, Christian Simon-Klar, Lars Friebe, Willm Hinrichs, Hanno Lieske, Peter Pirsch:
A compact and flexible multi-DSP system for real-time SAR applications. IGARSS 2003: 1657-1659 - [c51]Hans-Joachim Stolberg, Mladen Berekovic, Lars Friebe, Sören Moch, Mark Bernd Kulaczewski, Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing. VLSI-SOC 2003: 155-160 - 2002
- [j24]Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch:
Multicore system-on-chip architecture for MPEG-4 streaming video. IEEE Trans. Circuits Syst. Video Technol. 12(8): 688-699 (2002) - [j23]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing. J. VLSI Signal Process. 31(2): 157-171 (2002) - [c50]Helge Kloos, Jens Peter Wittenburg, Willm Hinrichs, Hanno Lieske, Lars Friebe, C. Klar, Peter Pirsch:
HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. ICASSP 2002: 3112-3115 - [c49]Jörn Jachalsky, M. Wahle, Peter Pirsch, Winfried Gehrke:
A flexible, fully configurable architecture for MPEG-2 video encoding. ICECS 2002: 1063-1066 - [c48]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch:
A platform-independent methodology for performance estimation of streaming media applications. ICME (2) 2002: 105-108 - [c47]Christian Simon-Klar, Lars Friebe, Helge Kloos, Hanno Lieske, Willm Hinrichs, Peter Pirsch:
A multi DSP board for real time SAR processing using the HiPAR-DSP 16. IGARSS 2002: 2750-2752 - [c46]Javier Martín-Langerwerf, Carsten Reuter, Holger Kropp, Peter Pirsch:
Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications. IEEE International Workshop on Rapid System Prototyping 2002: 60-65 - [c45]Peter Pirsch, Achim Freimann, C. Klar, Jens Peter Wittenburg:
Processor Architectures for Multimedia Applications. Embedded Processor Design Challenges 2002: 188-206 - [c44]Xun Mao, Wei Wang, Huimin Gong, Yan L. He, Jian Lou, Lu Yu, Qingdong Yao, Peter Pirsch:
Highly efficient simulation environment for HDTV video decoder in VLSI design. VCIP 2002: 1006-1014 - 2001
- [j22]Peter Pirsch, Carsten Reuter, Jens Peter Wittenburg, Mark Bernd Kulaczewski, Hans-Joachim Stolberg:
Architecture Concepts for Multimedia Signal Processing. J. VLSI Signal Process. 29(3): 157-165 (2001) - [c43]Mladen Berekovic, Hans-Joachim Stolberg, Peter Pirsch, Holger Runge:
A programmable co-porcessor for MPEG-4 video. ICASSP 2001: 1021-1024 - [c42]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge:
Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications. ICME 2001 - [c41]Mark Bernd Kulaczewski, Stefan Zimmerman, Erich Barke, Peter Pirsch:
CHIPDESIGN - A Novel Project-oriented Microelectronics Course. MSE 2001: 71-72 - 2000
- [j21]Carsten Reuter, Holger Kropp, Peter Pirsch:
Rapid Prototyping von Videosignalverarbeitungsverfahren (Rapid Prototyping of Video Processing Schemes). Informationstechnik Tech. Inform. 42(3): 5-9 (2000) - [j20]Willm Hinrichs, Jens Peter Wittenburg, Hanno Lieske, Helge Kloos, Martin Ohmacht, Peter Pirsch:
A 1.3-GOPS parallel DSP for high-performance image-processing applications. IEEE J. Solid State Circuits 35(7): 946-952 (2000) - [c40]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems. ASAP 2000: 15-24 - [c39]Klaus Herrmann, Sören Moch, Jörg Hilgenstock, Peter Pirsch:
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit. DFT 2000: 105-113 - [c38]Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo:
Co-processor architecture for MPEG-4 main profile visual compositing. ISCAS 2000: 180-183 - [c37]Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch, Holger Runge, Henning Möller, Johannes Kneip:
The M-PIRE MPEG-4 codec DSP and its macroblock engine. ISCAS 2000: 192-195 - [e1]Dimitrios Soudris, Peter Pirsch, Erich Barke:
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings. Lecture Notes in Computer Science 1918, Springer 2000, ISBN 3-540-41068-6 [contents]
1990 – 1999
- 1999
- [j19]Mohammad Ibrahim, Peter Pirsch, Johan McCanny:
Guest Editors' Introduction. J. VLSI Signal Process. 22(1): 5-6 (1999) - [j18]Mladen Berekovic, Helge Kloos, Peter Pirsch:
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications. J. VLSI Signal Process. 22(1): 31-43 (1999) - [j17]Mladen Berekovic, Hans-Joachim Stolberg, Mark Bernd Kulaczewski, Peter Pirsch, Henning Möller, Holger Runge, Johannes Kneip, Benno Stabernack:
Instruction Set Extensions for MPEG-4 Video. J. VLSI Signal Process. 23(1): 27-49 (1999) - [c36]Hans-Joachim Stolberg, Martin Ohmacht, Peter Pirsch:
Cellular Multiprocessor Arrays with Adaptive Resource Utilization. ACPC 1999: 480-489 - [c35]Helge Kloos, Mladen Berekovic, Peter Pirsch:
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen. ARCS 1999: 5-14 - [c34]Jens Peter Wittenburg, Willm Hinrichs, Martin Ohmacht, Hanno Lieske, Helge Kloos, Peter Pirsch:
HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. ARCS 1999: 15-21 - [c33]Holger Kropp, Carsten Reuter, Matthias Wiege, Tien-Toan Do, Peter Pirsch:
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. FPL 1999: 333-338 - [c32]Jörg Hilgenstock, Klaus Herrmann, Peter Pirsch:
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM. Great Lakes Symposium on VLSI 1999: 42-45 - [c31]Mladen Berekovic, K. Jacob, Peter Pirsch:
Architecture of a hardware module for MPEG-4 shape decoding. ISCAS (1) 1999: 157-160 - 1998
- [b2]Peter Pirsch:
Architectures for digital signal processing. Wiley 1998, ISBN 978-0-471-97145-0, pp. I-XI, 1-419 - [j16]Peter Pirsch, Hans-Joachim Stolberg:
VLSI implementations of image and video multimedia processing systems. IEEE Trans. Circuits Syst. Video Technol. 8(7): 878-891 (1998) - [j15]Mladen Berekovic, Peter Pirsch, Johannes Kneip:
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors. J. VLSI Signal Process. 20(1-2): 163-180 (1998) - [c30]Mladen Berekovic, Peter Pirsch:
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing. Computer Graphics International 1998: 411- - [c29]Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch:
A Video Signal Processor for MIMD Multiprocessing. DAC 1998: 50-55 - [c28]Jens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht, Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. DAC 1998: 56-61 - [c27]Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch:
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. FPL 1998: 441-445 - [c26]Mladen Berekovic, Rainer Frase, Peter Pirsch:
A flexible processor architecture for MPEG-4 image compositing. ICASSP 1998: 3153-3156 - [c25]Peter Pirsch, Hans-Joachim Stolberg:
VLSI architectures for multimedia. ICECS 1998: 3-11 - [c24]Mladen Berekovic, Peter Pirsch:
Architecture of a coprocessor module for image compositing. ICECS 1998: 203-206 - [c23]Holger Kropp, Carsten Reuter, Peter Pirsch:
The Video and Image Processing Emulation System VIPES. International Workshop on Rapid System Prototyping 1998: 170-175 - 1997
- [j14]Peter Pirsch, Hans-Joachim Stolberg, Yan-Kuang Chen, Sun-Yuan Kung:
Implementation of media processors. IEEE Signal Process. Mag. 14(4): 48-51 (1997) - [j13]Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. J. VLSI Signal Process. 16(1): 31-40 (1997) - [c22]Carsten Reuter, Markus Schwiegershausen, Peter Pirsch:
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. ASAP 1997: 294-303 - [c21]Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
Implementation of pipelined multipliers on Xilinx FPGAs. FPL 1997: 51-60 - [c20]Johannes Kneip, Mladen Berekovic, Peter Pirsch:
An algorithm-hardware-system approach to VLIW multimedia processors. MMSP 1997: 433-438 - 1996
- [b1]Peter Pirsch:
Architekturen der digitalen Signalverarbeitung. Informationstechnik, Teubner 1996, ISBN 978-3-519-06157-1, pp. I-IX, 1-368 - [c19]Markus Schwiegershausen, Holger Kropp, Peter Pirsch:
A system level HW/SW partitioning and optimization tool. EURO-DAC 1996: 120-125 - [c18]Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
A CAD tool for the optimization of video signal processor architectures. ICASSP 1996: 1244-1247 - [c17]Klaus Herrmann, Klaus Gaedke, Jörg Hilgenstock, Peter Pirsch:
Design of a development system for multimedia applications based on a single chip multiprocessor array. ICECS 1996: 1151-1154 - 1995
- [j12]Johannes Kneip, Martin Ohmacht, Karsten Rönner, Peter Pirsch:
Architecture and C++-programming environment of a highly parallel image signal processor. Microprocess. Microprogramming 41(5-6): 391-408 (1995) - [j11]Peter Pirsch, Nicolas Demassieux, Winfred Gehrke:
VLSI architectures for video compression-a survey. Proc. IEEE 83(2): 220-246 (1995) - [j10]Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. J. VLSI Signal Process. 11(1-2): 51-74 (1995) - [c16]Markus Schwiegershausen, Peter Pirsch:
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. EURO-DAC 1995: 8-13 - [c15]Peter Pirsch, Johannes Kneip, Karsten Rönner:
Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor. ISCAS 1995: 562-565 - [c14]Marco Winzker, Peter Pirsch, Jochen Reimers:
Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs. ISCAS 1995: 609-612 - [c13]Markus Schwiegershausen, Peter Pirsch:
A system level design methodology for the optimization of heterogeneous multiprocessors. ISSS 1995: 162-169 - 1994
- [c12]Johannes Kneip, Karsten Rönner, Peter Pirsch:
A data path array with shared memory as core of a high performance DSP. ASAP 1994: 271-282 - [c11]Winfried Gehrke, Richard Hoffer, Peter Pirsch:
A hierarchical multiprocessor architecture based on heterogeneous processors for video coding applications. ICASSP (2) 1994: 413-416 - 1993
- [j9]Hans Georg Musmann, Peter Pirsch:
Coding Algorithms and VLSI Implementations for Digital TV and HDTV Satellite Broadcasting. Eur. Trans. Telecommun. 4(1): 11-21 (1993) - [j8]V. Hecht, Karsten Rönner, Peter Pirsch:
A defect-tolerant systolic array implementation for real time image processing. J. VLSI Signal Process. 5(1): 37-47 (1993) - [j7]Klaus Gaedke, Hartwig Jeschke, Peter Pirsch:
A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications. J. VLSI Signal Process. 5(2-3): 159-169 (1993) - [c10]Jörg Schönfeld, Peter Pirsch:
Compact hardware realization for Hough based extraction of line segments in image sequences for vehicle guidance. ICASSP (1) 1993: 397-400 - [c9]Klaus Gaedke, Jens Franzen, Peter Pirsch:
A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic. ISCAS 1993: 1583-1586 - [c8]Peter Pirsch, Winfried Gehrke, Richard Hoffer:
A Hierarchical Multiprocessor Achitecture for Video Coding Applications. ISCAS 1993: 1750-1753 - [c7]Jörg Schönfeld, Peter Pirsch:
Single board image processing unit for vehicle guidance. VLSI 1993: 151-160 - 1992
- [j6]Hartwig Jeschke, Klaus Gaedke, Peter Pirsch:
Multiprocessor performance for real-time processing of video coding applications. IEEE Trans. Circuits Syst. Video Technol. 2(2): 221-230 (1992) - 1991
- [c6]V. Hecht, Karsten Rönner, Peter Pirsch:
A defect tolerant systolic array implementation for real time image processing. ASAP 1991: 25-39 - [c5]Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch:
Synthesis of intermediate memories for the data supply to processor arrays. Algorithms and Parallel VLSI Architectures 1991: 365-370 - [c4]Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch:
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. VLSI 1991: 297-306 - 1990
- [c3]Klaus Grüger, Peter Pirsch, Josef Kraus, Jochen Reimers:
VLSI components for a 560-Mbit/s HDTV codec. VCIP 1990
1980 – 1989
- 1989
- [c2]Thomas Komarek, Peter Pirsch:
VLSI architectures for block matching algorithms. ICASSP 1989: 2457-2460 - 1985
- [j5]Hans Georg Musmann, Peter Pirsch, Hans-Joachim Grallert:
Advances in picture coding. Proc. IEEE 73(4): 523-548 (1985) - [j4]Peter Pirsch:
Design of a DPCM codec for VLSI realization in CMOS technology. Proc. IEEE 73(4): 592-598 (1985) - 1984
- [c1]Paul Drews, Peter Pirsch, K. Schaper:
Circuit Technique for VLSI Design of a Video Codec. ICC (1) 1984: 250-255 - 1983
- [j3]Peter Pirsch, Arun N. Netravali:
Transmission of gray level images by multilevel dither techniques. Comput. Graph. 7(1): 31-44 (1983) - 1982
- [j2]Peter Pirsch:
Stability Conditions for DPCM Coders. IEEE Trans. Commun. 30(5): 1174-1184 (1982) - 1981
- [j1]Peter Pirsch:
Design of DPCM Quantizers for Video Signals Using Subjective Tests. IEEE Trans. Commun. 29(7): 990-1000 (1981)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 22:50 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
