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ORCIDMarkus Schwiegershausen
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1990 – 1999
- 1997
[b1]Markus Schwiegershausen:
Ein Verfahren zur Optimierung heterogener Multiprozessorsysteme mittels linearer Programmierung. University of Hanover, VDI-Verlag 1997, ISBN 3-18-351210-6, pp. 1-159- [c8]Carsten Reuter, Markus Schwiegershausen, Peter Pirsch:
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms. ASAP 1997: 294-303 - [c7]Tien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
Implementation of pipelined multipliers on Xilinx FPGAs. FPL 1997: 51-60 - 1996
- [c6]Markus Schwiegershausen, Holger Kropp, Peter Pirsch:
A system level HW/SW partitioning and optimization tool. EURO-DAC 1996: 120-125 - [c5]Holger Kropp, Markus Schwiegershausen, Peter Pirsch:
A CAD tool for the optimization of video signal processor architectures. ICASSP 1996: 1244-1247 - 1995
- [j1]Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques. J. VLSI Signal Process. 11(1-2): 51-74 (1995) - [c4]Markus Schwiegershausen, Peter Pirsch:
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes. EURO-DAC 1995: 8-13 - [c3]Markus Schwiegershausen, Peter Pirsch:
A system level design methodology for the optimization of heterogeneous multiprocessors. ISSS 1995: 162-169 - 1991
- [c2]Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch:
Synthesis of intermediate memories for the data supply to processor arrays. Algorithms and Parallel VLSI Architectures 1991: 365-370 - [c1]Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch:
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. VLSI 1991: 297-306
Coauthor Index
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