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ORCIDASAP 1991: Barcelona, Spain
- Application Specific Array Processors, 1991. Proceedings of the International Conference on, Barcelona, Spain, 2-4 Sept., 1991. IEEE 1991, ISBN 0-8186-9237-5
- Earl E. Swartzlander Jr.:
The case for application specific computing. 2-9 - Guy Corbaz, Jean Duprat, Bertrand Hochet, Jean-Michel Muller
:
Implementation of a VLSI polynomial evaluator for real-time applications. 13-24 - V. Hecht, Karsten Rönner, Peter Pirsch:
A defect tolerant systolic array implementation for real time image processing. 25-39 - Jan Rosseel, Francky Catthoor, Hugo De Man:
The systematic design of a motion estimation array architecture. 40-54 - Agustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García:
Transformation of systolic algorithms for interleaving partitions. 56-71 - Uwe Vehlies:
Mapping different node types of dependence graphs into the same processing element. 72-86 - Angelos P. Varvitsiotis, Sergios Theodoridis, Rami G. Melhem:
Mapping FIR filtering on systolic rings. 87-101 - Jeff Robinson, Keith Rouse, Paul Jordan, Terry Montlick:
The missing dimension in real-time signal processing architectures. 104-115 - Rajinder Jit Singh, John V. McCanny:
A wave digital filter three-port adaptor with fine grained pipelining. 116-128 - Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin:
The Arithmetic Cube: error analysis and simulation. 129-143 - E. T. Chow, Tim Hunkapiller, J. Peterson, Michael S. Waterman:
Biological information signal processor. 144-160 - K. Wojtek Przytula:
Parallel digital implementations of neural networks. 162-176 - Ricardo Telichevesky, Prathima Agrawal, John A. Trotter:
Partitioning schemes for circuit simulation on a multiprocessor array. 177-183 - Wei-Ming Lin, Viktor K. Prasanna:
Parallel implementations of discrete relaxation technique on fixed size processor arrays. 184-198 - Manfred Schimmler:
Parallel strong orientation on a mesh connected computer. 199-211 - Teresa H.-Y. Meng, Andy C. Hung:
Parallel array architectures for motion estimation. 214-235 - Chie Dou, Shao-Ming Wu:
CAPMA: a content-addressable pattern match architecture for production systems. 236-248 - John A. Vlontzos:
High speed implementation of 1-D and 2-D morphological operations. 249-262 - Wayne W. C. Luk:
Pipelining and transposing heterogeneous array circuits. 263-277 - Jaime H. Moreno, Miguel E. Figueroa:
A decoupled access/execute processor for matrix algorithms: architecture and programming. 281-295 - Tanguy Risset, Yves Robert:
Uniform but non-local DAGS: a trade-off between pure systolic and SIMD solutions. 296-308 - Vijay Karamcheti, Miroslaw Malek:
A TSP engine for performing tabu search. 309-321 - Catherine Dezan, Eric Gautrin, Hervé Le Verge, Patrice Quinton, Yannick Saouter:
Synthesis of systolic arrays by equation transformations. 324-337 - Nam Ling, Fuyau Lin, Timothy K. Shih, Ruth E. Davis:
Automatic formal verification of systolic array designs. 338-354 - Edward A. Lee:
Consistency in dataflow graphs. 355-369 - Alain Darte, Tanguy Risset, Yves Robert:
Synthesizing systolic arrays: some recent developments. 372-386 - Jens Franzen:
A design method for on-line reconfigurable array processors. 387-401 - Jichun Bu, Ed F. Deprettere:
Processor clustering for the design of optimal fixed-size systolic arrays. 402-413 - O. C. McNally, John V. McCanny, Roger F. Woods:
A 40 megasample IIR filter chip. 416-430 - Dominique Houzet, Jean-Luc Basille, Jean-Yves Latil:
GFLOPS: a general flexible linearly organized parallel structure for images. 431-444 - Yen-Chun Lin, Yu-Ho Cheng:
Fast generation of long sorted runs for sorting a large file. 445-456 - Rumen Andonov, Frédéric Gruau:
A modular systolic 2-D torus for the general knapsack problem. 458-472 - José L. Hueso, Gloria Martínez, Vicente Hernández:
A systolic algorithm for the triangular Stein equation. 473-484 - S. Erlich, K. Yao:
Systolic architecture for adaptive eigenstructure decomposition based on simultaneous iteration method. 485-495
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