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ORCIDJaime H. Moreno
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- affiliation: IBM
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2010 – 2019
- 2019
[c18]Jaime H. Moreno, Hui-Fang Wen:
Benchmarking Summit and Sierra Supercomputers : From Proposal to Acceptance. HPCS 2019: 428-435- [c17]Ian Karlin, Yoonho Park, Bronis R. de Supinski, Peng Wang, Bert Still, David Beckingsale, Robert Blake, Tong Chen, Guojing Cong, Carlos H. A. Costa, Johann Dahm, Giacomo Domeniconi, Thomas Epperly, Aaron Fisher, Sara Kokkila Schumacher
, Steven H. Langer, Hai Le, Eun Kyung Lee, Naoya Maruyama, Xinyu Que, David F. Richards, Björn Sjögreen, Jonathan Wong, Carol S. Woodward, Ulrike Meier Yang, Xiaohua Zhang, Bob Anderson, David Appelhans, Levi Barnes, Peter D. Barnes Jr., Sorin Bastea, David Böhme, Jamie A. Bramwell, James M. Brase, José R. Brunheroto, Barry Chen, Charway R. Cooper, Tony Degroot, Robert D. Falgout, Todd Gamblin, David J. Gardner, James N. Glosli, John A. Gunnels, Max P. Katz, Tzanio V. Kolev, I-Feng W. Kuo, Matthew P. LeGendre, Ruipeng Li, Pei-Hung Lin, Shelby Lockhart, Kathleen McCandless, Claudia Misale, Jaime H. Moreno, Rob Neely, Jarom Nelson, Rao Nimmakayala, Kathryn M. O'Brien, Kevin O'Brien, Ramesh Pankajakshan, Roger Pearce, Slaven Peles, Phil Regier, Steven C. Rennich, Martin Schulz, Howard Scott, James C. Sexton, Kathleen Shoga, Shiv Sundram, Guillaume Thomas-Collignon, Brian Van Essen, Alexey Voronin, Bob Walkup, Lu Wang, Chris Ward, Hui-Fang Wen, Daniel A. White, Christopher Young, Cyril Zeller, Edward Zywicz:
Preparation and optimization of a diverse workload for a large-scale heterogeneous system. SC 2019: 32:1-32:17 - 2016
- [j10]Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, Cristian Estan:
Near-Memory Data Services. IEEE Micro 36(1): 6-13 (2016) - 2015
- [j9]Ravi Nair, Samuel Antão, Carlo Bertolli, Pradip Bose, José R. Brunheroto, Tong Chen, Chen-Yong Cher, Carlos H. A. Costa, J. Doi, Constantinos Evangelinos, Bruce M. Fleischer, Thomas W. Fox, Diego S. Gallo, Leopold Grinberg, John A. Gunnels, Arpith C. Jacob, P. Jacob, Hans M. Jacobson, Tejas Karkhanis, C. Kim, Jaime H. Moreno, John K. O'Brien, Martin Ohmacht, Yoonho Park, Daniel A. Prener, Bryan S. Rosenburg, Kyung Dong Ryu, Olivier Sallenave, Mauricio J. Serrano, P. D. M. Siegl, Krishnan Sugavanam, Zehra Sura:
Active Memory Cube: A processing-in-memory architecture for exascale systems. IBM J. Res. Dev. 59(2/3) (2015) - 2014
- [j8]Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime H. Moreno, Richard Murphy, Ravi Nair, Steven Swanson:
Near-Data Processing: Insights from a MICRO-46 Workshop. IEEE Micro 34(4): 36-42 (2014) - [c16]Philip G. Emma, Alper Buyuktosunoglu, Michael B. Healy, Krishnan Kailas, Valentin Puente, Roy Yu, Allan Hartstein, Pradip Bose, Jaime H. Moreno, Eren Kursun:
3D stacking of high-performance processors. HPCA 2014: 500-511 - 2010
- [c15]Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun:
Extreme scale computing: Challenges and opportunities. HPCA 2010: 1 - [c14]Josep Torrellas, Bill Gropp, Jaime H. Moreno, Kunle Olukotun, Vivek Sarkar:
Extreme scale computing: challenges and opportunities. PPoPP 2010: 101-102
2000 – 2009
- 2009
- [c13]John P. Karidis, José E. Moreira, Jaime H. Moreno:
True value: assessing and optimizing the cost of computing at the data center level. Conf. Computing Frontiers 2009: 185-192 - 2006
- [c12]Jaime H. Moreno:
Chip-level integration: the new frontier for microprocessor architecture. SPAA 2006: 328 - 2004
- [c11]Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno:
Design methodology for semi custom processor cores. ACM Great Lakes Symposium on VLSI 2004: 448-452 - 2003
- [j7]Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter:
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47(2-3): 299-326 (2003) - [c10]Hillery C. Hunter, Jaime H. Moreno:
A new look at exploiting data parallelism in embedded systems. CASES 2003: 159-169 - [c9]Jeff H. Derby, Jaime H. Moreno:
A high-performance embedded DSP core with novel SIMD features. ICASSP (2) 2003: 301-304 - [c8]Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325 - [e1]Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003. ACM 2003, ISBN 1-58113-676-5 [contents]
1990 – 1999
- 1999
- [j6]Mayan Moudgill, John-David Wellman, Jaime H. Moreno:
Environment for PowerPC microarchitecture exploration. IEEE Micro 19(3): 15-25 (1999) - [c7]Mayan Moudgill, Pradip Bose, Jaime H. Moreno:
Validation of Turandot, a fast processor model for microarchitecture exploration. IPCCC 1999: 451-457 - 1997
- [j5]Jaime H. Moreno, Mayan Moudgill, Kemal Ebcioglu, Erik R. Altman, C. Brian Hall, Rene Miranda, Shyh-Kwei Chen, Arkady Polyak:
Simulation/evaluation environment for a VLIW processor architecture. IBM J. Res. Dev. 41(3): 287-302 (1997) - [c6]Jaime H. Moreno, Mayan Moudgill:
Scalable Instruction-Level Parallelism Through Tree-Instructions. International Conference on Supercomputing 1997: 1-11 - 1993
- [j4]Tomás Lang, Jaime H. Moreno:
Introduction. J. VLSI Signal Process. 5(1): 6 (1993) - 1992
- [c5]Dinh Lê, Milos D. Ercegovac, Tomás Lang, Jaime H. Moreno:
MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs. ASAP 1992: 511-525 - 1991
- [j3]Jaime H. Moreno, Miguel E. Figueroa, Tomás Lang:
Linear pseudosystolic array for partitioned matrix algorithms. J. VLSI Signal Process. 3(3): 201-214 (1991) - [c4]Jaime H. Moreno, Miguel E. Figueroa:
A decoupled access/execute processor for matrix algorithms: architecture and programming. ASAP 1991: 281-295 - 1990
- [j2]Jaime H. Moreno, Tomás Lang:
Matrix Computations on Systolic-Type Meshes. Computer 23(4): 32-51 (1990) - [c3]Jaime H. Moreno, Tomás Lang:
A graph-based approach to map matrix algorithms onto local-access processor arrays. ASAP 1990: 641-652
1980 – 1989
- 1989
- [j1]Jaime H. Moreno, Tomás Lang:
Comments on 'A systolic array for computing BA-1'. IEEE Trans. Acoust. Speech Signal Process. 37(11): 1786-1789 (1989) - 1988
- [c2]Jaime H. Moreno, Tomás Lang:
Graph-based Partitioning of Matrix Algorithms for Systolic Arrays: Application to Transitive Closure. ICPP (1) 1988: 28-31 - 1986
- [c1]Jaime H. Moreno, Tomás Lang:
Replication and Pipelining in Multiple-Instance Algorithms. ICPP 1986: 285-292
Coauthor Index
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