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ORCIDJosep Torrellas
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- affiliation: University of Illinois at Urbana-Champaign, Urbana, IL, USA
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2020 – today
- 2024
[j41]Gerasimos Gerogiannis
, Josep Torrellas:
Practical Online Reinforcement Learning for Microprocessors With Micro-Armed Bandit. IEEE Micro 44(4): 80-87 (2024)- [c230]Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas:
FriendlyFoe: Adversarial Machine Learning as a Practical Architectural Defense against Side Channel Attacks. PACT 2024: 338-350 - [c229]Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
Everywhere All at Once: Co-Location Attacks on Public Cloud FaaS. ASPLOS (1) 2024: 133-149 - [c228]Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud. ASPLOS (2) 2024: 582-600 - [c227]Charles Block, Gerasimos Gerogiannis, Charith Mendis, Ariful Azad, Josep Torrellas:
Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM. ASPLOS (2) 2024: 1200-1217 - [c226]Antonis Psistakis, Fabien Chaix, Josep Torrellas:
MINOS: Distributed Consistency and Persistency Protocol Implementation & Offloading to SmartNICs. HPCA 2024: 1-17 - [c225]Gerasimos Gerogiannis, Sriram Aananthakrishnan, Josep Torrellas, Ibrahim Hur:
HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures. HPCA 2024: 1012-1028 - [c224]Jovan Stojkovic, Nikoleta Iliakopoulou, Tianyin Xu, Hubertus Franke, Josep Torrellas:
EcoFaaS: Rethinking the Design of Serverless Environments for Energy Efficiency. ISCA 2024: 471-486 - [c223]Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas:
HADES: Hardware-Assisted Distributed Transactions in the Age of Fast Networks and SmartNICs. ISCA 2024: 785-800 - [c222]Jovan Stojkovic, Esha Choukse, Enrique Saurez, Íñigo Goiri, Josep Torrellas:
Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments. MICRO 2024: 1397-1412 - [c221]Isuru Ranawaka, Md Taufique Hussain, Charles Block, Gerasimos Gerogiannis, Josep Torrellas, Ariful Azad:
Distributed-Memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication. SC 2024: 46 - [i19]Jovan Stojkovic, Esha Choukse, Chaojie Zhang, Íñigo Goiri, Josep Torrellas:
Towards Greener LLMs: Bringing Energy-Efficiency to the Forefront of LLM Inference. CoRR abs/2403.20306 (2024) - [i18]Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud (Extended Version). CoRR abs/2405.12469 (2024) - [i17]Jovan Stojkovic, Chaojie Zhang, Íñigo Goiri, Josep Torrellas, Esha Choukse:
DynamoLLM: Designing LLM Inference Clusters for Performance and Energy Efficiency. CoRR abs/2408.00741 (2024) - [i16]Isuru Ranawaka, Md Taufique Hussain, Charles Block, Gerasimos Gerogiannis, Josep Torrellas, Ariful Azad:
Distributed-Memory Parallel Algorithms for Sparse Matrix and Sparse Tall-and-Skinny Matrix Multiplication. CoRR abs/2408.11988 (2024) - [i15]Deming Chen, Alaa Youssef, Ruchi Pendse, André Schleife, Bryan K. Clark, Hendrik F. Hamann, Jingrui He, Teodoro Laino, Lav R. Varshney, Yuxiong Wang, Avirup Sil, Reyhaneh Jabbarvand, Tianyin Xu, Volodymyr V. Kindratenko, Carlos H. A. Costa, Sarita V. Adve, Charith Mendis, Minjia Zhang, Santiago Núñez-Corrales, Raghu K. Ganti, Mudhakar Srivatsa, Nam Sung Kim, Josep Torrellas, Jian Huang, Seetharami R. Seelam, Klara Nahrstedt, Tarek F. Abdelzaher, Tamar Eilam, Huimin Zhao, Matteo Manica, Ravishankar K. Iyer, Martin Hirzel, Vikram S. Adve, Darko Marinov, Hubertus Franke, Hanghang Tong, Elizabeth A. Ainsworth, Han Zhao, Deepak Vasisht, Minh Do, Fábio Oliveira, Giovanni Pacifici, Ruchir Puri, Priya Nagpurkar:
Transforming the Hybrid Cloud for Emerging AI Workloads. CoRR abs/2411.13239 (2024) - [i14]Nikoleta Iliakopoulou, Jovan Stojkovic, Chloe Alverti, Tianyin Xu, Hubertus Franke, Josep Torrellas:
Chameleon: Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments. CoRR abs/2411.17741 (2024) - 2023
- [c220]Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes. ASPLOS (3) 2023: 771-788 - [c219]Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas:
SpecFaaS: Accelerating Serverless Applications with Speculative Function Execution. HPCA 2023: 814-827 - [c218]Jovan Stojkovic, Namrata Mantri, Dimitrios Skarlatos, Tianyin Xu, Josep Torrellas:
Memory-Efficient Hashed Page Tables. HPCA 2023: 1221-1235 - [c217]Gerasimos Gerogiannis, Serif Yesil, Damitha Lenadora, Dingyuan Cao, Charith Mendis, Josep Torrellas:
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM. ISCA 2023: 19:1-19:15 - [c216]Jovan Stojkovic, Chunao Liu, Muhammad Shahbaz, Josep Torrellas:
μManycore: A Cloud-Native CPU for Tail at Scale. ISCA 2023: 33:1-33:15 - [c215]Jovan Stojkovic, Tianyin Xu, Hubertus Franke, Josep Torrellas:
MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency. ISCA 2023: 34:1-34:15 - [c214]Gerasimos Gerogiannis, Josep Torrellas:
Micro-Armed Bandit: Lightweight & Reusable Reinforcement Learning for Microarchitecture Decision-Making. MICRO 2023: 698-713 - [c213]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning. PPoPP 2023: 329-341 - [i13]Hyoungwook Nam, Raghavendra Pradyumna Pothukuchi, Bo Li, Nam Sung Kim, Josep Torrellas:
Defensive ML: Defending Architectural Side-channels with Adversarial Obfuscation. CoRR abs/2302.01474 (2023) - [i12]Damitha Lenadora, Vimarsh Sathia, Gerasimos Gerogiannis, Serif Yesil, Josep Torrellas, Charith Mendis:
Input-sensitive dense-sparse primitive compositions for GNN acceleration. CoRR abs/2306.15155 (2023) - 2022
- [j40]Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas:
Distributed Data Persistency. IEEE Micro 42(4): 107-115 (2022) - [c212]Jovan Stojkovic, Dimitrios Skarlatos, Apostolos Kokolis, Tianyin Xu, Josep Torrellas:
Parallel virtualized memory translation with nested elastic cuckoo page tables. ASPLOS 2022: 84-97 - [c211]Zirui Neil Zhao, Houxiang Ji, Adam Morrison, Darko Marinov, Josep Torrellas:
Pinned loads: taming speculative loads in secure processors. ASPLOS 2022: 314-328 - [c210]Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos:
Cloak: tolerating non-volatile cache read latency. ICS 2022: 22:1-22:13 - [c209]Serif Yesil, José E. Moreira, Josep Torrellas:
Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques. ICS 2022: 27:1-27:14 - [c208]Zhangxiaowen Gong, Houxiang Ji, Yao Yao, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas:
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. ISCA 2022: 916-931 - [c207]Zirui Neil Zhao, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
Binoculars: Contention-Based Side-Channel Attacks Exploiting the Page Walker. USENIX Security Symposium 2022: 699-716 - [i11]Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang:
UniHeap: Managing Persistent Objects Across Managed Runtimes for Non-Volatile Memory. CoRR abs/2205.06444 (2022) - 2021
- [j39]Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher:
Speculative taint tracking (STT): a comprehensive protection for speculatively accessed data. Commun. ACM 64(12): 105-112 (2021) - [j38]Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, Josep Torrellas:
BabelFish: Fusing Address Translations for Containers. IEEE Micro 41(3): 57-62 (2021) - [c206]Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Neil Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos V. Rozas, Adam Morrison, Frank McKeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa R. Alameldeen:
Speculative interference attacks: breaking invisible speculation schemes. ASPLOS 2021: 1046-1060 - [c205]Dimitrios Skarlatos, Zirui Neil Zhao, Riccardo Paccagnella, Christopher W. Fletcher, Josep Torrellas:
Jamais vu: thwarting microarchitectural replay attacks. ASPLOS 2021: 1061-1076 - [c204]Antonio Franques, Sergi Abadal, Haitham Hassanieh, Josep Torrellas:
Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores. DATE 2021: 1657-1662 - [c203]Antonio Franques, Apostolos Kokolis, Sergi Abadal, Vimuth Fernando, Sasa Misailovic, Josep Torrellas:
WiDir: A Wireless-Enabled Directory Cache Coherence Protocol. HPCA 2021: 304-317 - [c202]Thomas Shull, Ilias Vougioukas, Nikos Nikoleris, Wendy Elsasser, Josep Torrellas:
Execution Dependence Extension (EDE): ISA Support for Eliminating Fences. ISCA 2021: 456-469 - [c201]Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Alexander G. Schwing, Josep Torrellas:
Maya: Using Formal Control to Obfuscate Power Side Channels. ISCA 2021: 888-901 - [c200]Apostolos Kokolis, Antonis Psistakis, Benjamin Reidys, Jian Huang, Josep Torrellas:
Distributed Data Persistency. MICRO 2021: 71-85 - [c199]Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Sergi Abadal, Josep Torrellas, Haitham Hassanieh:
One Protocol to Rule Them All: Wireless Network-on-Chip using Deep Reinforcement Learning. NSDI 2021: 973-989 - [c198]Daixuan Li, Benjamin Reidys, Jinghan Sun, Thomas Shull, Josep Torrellas, Jian Huang:
UniHeap: managing persistent objects across managed runtimes for non-volatile memory. SYSTOR 2021: 7:1-7:12 - [i10]Apostolos Kokolis, Namrata Mantri, Shrikanth Ganapathy, Josep Torrellas, John Kalamatianos:
A Method for Hiding the Increased Non-Volatile Cache Read Latency. CoRR abs/2112.10632 (2021) - 2020
- [j37]Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher:
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data. IEEE Micro 40(3): 81-90 (2020) - [j36]Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher:
MicroScope: Enabling Microarchitectural Replay Attacks. IEEE Micro 40(3): 91-98 (2020) - [j35]Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. IEEE Trans. Commun. 68(5): 3247-3258 (2020) - [c197]Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas:
SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. PACT 2020: 279-292 - [c196]Dimitrios Skarlatos, Apostolos Kokolis, Tianyin Xu, Josep Torrellas:
Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism. ASPLOS 2020: 1093-1108 - [c195]Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos, Sasa Misailovic, Adam Morrison, Josep Torrellas:
V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging. ICS 2020: 9:1-9:13 - [c194]Azin Heidarshenas, Tanmay Gangwani, Serif Yesil, Adam Morrison, Josep Torrellas:
Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors. ICS 2020: 18:1-18:13 - [c193]Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, Josep Torrellas:
BabelFish: Fusing Address Translations for Containers. ISCA 2020: 501-514 - [c192]Jiyong Yu, Namrata Mantri, Josep Torrellas, Adam Morrison, Christopher W. Fletcher:
Speculative Data-Oblivious Execution: Mobilizing Safe Prediction For Safe and Efficient Speculative Execution. ISCA 2020: 707-720 - [c191]Dimitrios Skarlatos, Qingrong Chen, Jianyan Chen, Tianyin Xu, Josep Torrellas:
Draco: Architectural and Operating System Support for System Call Security. MICRO 2020: 42-57 - [c190]Apostolos Kokolis, Thomas Shull, Jian Huang, Josep Torrellas:
P-INSPECT: Architectural Support for Programmable Non-Volatile Memory Frameworks. MICRO 2020: 509-524 - [c189]Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Sara S. Baghsorkhi, Josep Torrellas:
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. MICRO 2020: 796-810 - [c188]Zirui Neil Zhao, Houxiang Ji, Mengjia Yan, Jiyong Yu, Christopher W. Fletcher, Adam Morrison, Darko Marinov, Josep Torrellas:
Speculation Invariance (InvarSpec): Faster Safe Execution Through Program Analysis. MICRO 2020: 1138-1152 - [c187]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization. SC 2020: 86 - [c186]Suraj Jog, Zikun Liu, Antonio Franques, Vimuth Fernando, Haitham Hassanieh, Sergi Abadal, Josep Torrellas:
Millimeter wave wireless network on chip using deep reinforcement learning. SIGCOMM Posters and Demos 2020: 70-72 - [c185]Mengjia Yan, Christopher W. Fletcher, Josep Torrellas:
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures. USENIX Security Symposium 2020: 2003-2020 - [i9]Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Neil Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos V. Rozas, Adam Morrison, Frank McKeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa R. Alameldeen:
Speculative Interference Attacks: Breaking Invisible Speculation Schemes. CoRR abs/2007.11818 (2020)
2010 – 2019
- 2019
- [c184]Vimuth Fernando, Antonio Franques, Sergi Abadal, Sasa Misailovic, Josep Torrellas:
Replica: A Wireless Manycore for Communication-Intensive and Approximate Data. ASPLOS 2019: 849-863 - [c183]Thomas Shull, Jiho Choi, María Jesús Garzarán, Josep Torrellas:
NoMap: Speeding-Up JavaScript Using Hardware Transactional Memory. HPCA 2019: 412-425 - [c182]Apostolos Kokolis, Dimitrios Skarlatos, Josep Torrellas:
PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems. HPCA 2019: 596-608 - [c181]Dimitrios Skarlatos, Mengjia Yan, Bhargava Gopireddy, Read Sprabery, Josep Torrellas, Christopher W. Fletcher:
MicroScope: enabling microarchitectural replay attacks. ISCA 2019: 318-331 - [c180]Mengjia Yan, Jen-Yang Wen, Christopher W. Fletcher, Josep Torrellas:
SecDir: a secure directory to defeat directory side-channel attacks. ISCA 2019: 332-345 - [c179]Bhargava Gopireddy, Josep Torrellas:
Designing vertical processors in monolithic 3D. ISCA 2019: 643-656 - [c178]Sergi Abadal, Adrián Marruedo, Antonio Franques, Hamidreza Taghvaee, Albert Cabellos-Aparicio, Jin Zhou, Josep Torrellas, Eduard Alarcón:
Opportunistic Beamforming in Wireless Network-on-Chip. ISCAS 2019: 1-5 - [c177]Raghavendra Pradyumna Pothukuchi, Joseph L. Greathouse, Karthik Rao, Christopher Erb, Leonardo Piga, Petros G. Voulgaris, Josep Torrellas:
Tangram: Integrated Control of Heterogeneous Computers. MICRO 2019: 384-398 - [c176]Jiyong Yu, Mengjia Yan, Artem Khyzha, Adam Morrison, Josep Torrellas, Christopher W. Fletcher:
Speculative Taint Tracking (STT): A Comprehensive Protection for Speculatively Accessed Data. MICRO 2019: 954-968 - [c175]Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy (Corrigendum). MICRO 2019: 1076 - [c174]Thomas Shull, Jian Huang, Josep Torrellas:
AutoPersist: an easy-to-use Java NVM framework based on reachability. PLDI 2019: 316-332 - [c173]Jiho Choi, Thomas Shull, Josep Torrellas:
Reusable inline caching for JavaScript performance. PLDI 2019: 889-901 - [c172]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
Understanding priority-based scheduling of graph algorithms on a shared-memory platform. SC 2019: 46:1-46:14 - [c171]Mengjia Yan, Read Sprabery, Bhargava Gopireddy, Christopher W. Fletcher, Roy H. Campbell, Josep Torrellas:
Attack Directories, Not Caches: Side Channel Attacks in a Non-Inclusive World. IEEE Symposium on Security and Privacy 2019: 888-904 - [c170]Thomas Shull, Jian Huang, Josep Torrellas:
QuickCheck: using speculation to reduce the overhead of checks in NVM frameworks. VEE 2019: 137-151 - [i8]Xavier Timoneda, Sergi Abadal, Antonio Franques, Dionysios Manessis, Jin Zhou, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication. CoRR abs/1901.04291 (2019) - [i7]Sergi Abadal, Adrián Marruedo, Antonio Franques, Hamidreza Taghvaee, Albert Cabellos-Aparicio, Jin Zhou, Josep Torrellas, Eduard Alarcón:
Opportunistic Beamforming in Wireless Network-on-Chip. CoRR abs/1906.05361 (2019) - [i6]Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas:
Maya: Falsifying Power Sidechannels with Operating System Support. CoRR abs/1907.09440 (2019) - [i5]Zhangxiaowen Gong, Houxiang Ji, Christopher W. Fletcher, Christopher J. Hughes, Josep Torrellas:
SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. CoRR abs/1911.10175 (2019) - 2018
- [j34]Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
Medium Access Control in Wireless Network-on-Chip: A Context Analysis. IEEE Commun. Mag. 56(6): 172-178 (2018) - [j33]Zhangxiaowen Gong, Zhi Chen, Justin Josef Szaday, David C. Wong, Zehra Sura, Neftali Watkinson, Saeed Maleki, David A. Padua, Alexander V. Veidenbaum, Alexandru Nicolau, Josep Torrellas:
An empirical study of the effect of source-level loop transformations on compiler stability. Proc. ACM Program. Lang. 2(OOPSLA): 126:1-126:29 (2018) - [j32]Sergi Abadal, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture. IEEE Trans. Parallel Distributed Syst. 29(3): 628-641 (2018) - [c169]Jiho Choi, Thomas Shull, Josep Torrellas:
Biased reference counting: minimizing atomic operations in garbage collection. PACT 2018: 35:1-35:12 - [c168]Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas:
Structured Singular Value Control for Modular Resource Management in Multilayer Computers. CDC 2018: 5121-5127 - [c167]Yasser Shalabi, Mengjia Yan, Nima Honarmand, Ruby B. Lee, Josep Torrellas:
Record-Replay Architecture as a General Security Framework. HPCA 2018: 180-193 - [c166]Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas:
Yukta: Multilayer Resource Controllers to Maximize Efficiency. ISCA 2018: 505-518 - [c165]Bhargava Gopireddy, Dimitrios Skarlatos, Wenjuan Zhu, Josep Torrellas:
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs. ISCA 2018: 802-815 - [c164]Xavier Timoneda, Sergi Abadal, Albert Cabellos-Aparicio, Dionysios Manessis, Jin Zhou, Antonio Franques, Josep Torrellas, Eduard Alarcón:
Millimeter-Wave Propagation within a Computer Chip Package. ISCAS 2018: 1-5 - [c163]Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrellas:
InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy. MICRO 2018: 428-441 - [c162]Thomas Shull, Jian Huang, Josep Torrellas:
Defining a high-level programming model for emerging NVRAM technologies. ManLang 2018: 11:1-11:7 - [i4]Sergi Abadal, Albert Mestres, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
Medium Access Control in Wireless Network-on-Chip: A Context Analysis. CoRR abs/1806.06294 (2018) - [i3]Xavier Timoneda, Sergi Abadal, Albert Cabellos-Aparicio, Dionysios Manessis, Jin Zhou, Antonio Franques, Josep Torrellas, Eduard Alarcón:
Millimeter-Wave Propagation within a Computer Chip Package. CoRR abs/1807.09472 (2018) - [i2]Mengjia Yan, Christopher W. Fletcher, Josep Torrellas:
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures. CoRR abs/1808.04761 (2018) - 2017
- [j31]Amirhossein Mirhosseini, Aditya Agrawal, Josep Torrellas:
Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery. IEEE Comput. Archit. Lett. 16(2): 153-157 (2017) - [c161]Raghavendra Pradyumna Pothukuchi, Amin Ansari, Bhargava Gopireddy, Josep Torrellas:
Sthira: A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency. PACT 2017: 260-272 - [c160]Raghavendra Pradyumna Pothukuchi, Sweta Yamini Pothukuchi, Petros G. Voulgaris, Josep Torrellas:
Multilayer Compute Resource Management with Robust Control Theory. PACT 2017: 376 - [c159]Zhi Chen, Zhangxiaowen Gong, Justin Josef Szaday, David C. Wong, David A. Padua, Alexandru Nicolau, Alexander V. Veidenbaum, Neftali Watkinson, Zehra Sura, Saeed Maleki, Josep Torrellas, Gerald DeJong:
LORE: A loop repository for the evaluation of compilers. IISWC 2017: 219-228 - [c158]Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas:
Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks. ISCA 2017: 347-360 - [c157]Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas:
ShortCut: Architectural Support for Fast Object Access in Scripting Languages. ISCA 2017: 494-506 - [c156]Dimitrios Skarlatos, Nam Sung Kim, Josep Torrellas:
Pageforge: a near-memory content-aware page-merging architecture. MICRO 2017: 302-314 - [c155]Aditya Agrawal, Josep Torrellas, Sachin Idgunji:
Xylem: enhancing vertical thermal conduction in 3D processor-memory stacks. MICRO 2017: 546-559 - 2016
- [c154]Sanyam Mehta, Josep Torrellas:
WearCore: A Core for Wearable Workloads. PACT 2016: 153-164 - [c153]Sergi Abadal, Albert Cabellos-Aparicio, Eduard Alarcón, Josep Torrellas:
WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication. ASPLOS 2016: 3-17 - [c152]Tanmay Gangwani, Adam Morrison, Josep Torrellas:
CASPAR: Breaking Serialization in Lock-Free Multicore Synchronization. ASPLOS 2016: 789-804 - [c151]Josep Torrellas:
Toward Extreme-Scale Processor Chips. HiPC 2016: 290 - [c150]Sanket Tavarageri, Wooil Kim, Josep Torrellas, P. Sadayappan:
Compiler Support for Software Cache Coherence. HiPC 2016: 341-350 - [c149]Yuelu Duan, David A. Koufaty, Josep Torrellas:
SCsafe: Logging sequential consistency violations continuously and precisely. HPCA 2016: 249-260 - [c148]Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, Asit K. Mishra:
ScalCore: Designing a core for voltage scalability. HPCA 2016: 681-693 - [c147]Wooil Kim, Sanket Tavarageri, P. Sadayappan, Josep Torrellas:
Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy. IPDPS 2016: 555-565 - [c146]Raghavendra Pradyumna Pothukuchi, Amin Ansari, Petros G. Voulgaris, Josep Torrellas:
Using Multiple Input, Multiple Output Formal Control to Maximize Resource Efficiency in Architectures. ISCA 2016: 658-670 - [c145]Albert Mestres, Sergi Abadal, Josep Torrellas, Eduard Alarcón, Albert Cabellos-Aparicio:
A MAC protocol for Reliable Broadcast Communications in Wireless Network-on-Chip. NoCArc@MICRO 2016: 21-26 - [c144]Mengjia Yan, Yasser Shalabi, Josep Torrellas:
ReplayConfusion: Detecting cache-based covert channel attacks using record and replay. MICRO 2016: 39:1-39:14 - [c143]Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas:
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO 2016: 54:1-54:12 - [p1]Josep Torrellas:
Many-Core Architecture for NTC: Energy Efficiency from the Ground Up. Near Threshold Computing 2016: 21-33 - [i1]Mark D. Hill, Sarita V. Adve, Luis Ceze, Mary Jane Irwin, David R. Kaeli, Margaret Martonosi, Josep Torrellas, Thomas F. Wenisch, David A. Wood, Katherine A. Yelick:
21st Century Computer Architecture. CoRR abs/1609.06756 (2016) - 2015
- [c142]Yuelu Duan, Nima Honarmand, Josep Torrellas:
Asymmetric Memory Fences: Optimizing Both Performance and Implementability. ASPLOS 2015: 531-543 - 2014
- [c141]Nima Honarmand, Josep Torrellas:
RelaxReplay: record and replay for relaxed-consistency multiprocessors. ASPLOS 2014: 223-238 - [c140]Josep Torrellas:
Extreme-scale computer architecture: Energy efficiency from the ground up‡. DATE 2014: 1-5 - [c139]Aditya Agrawal, Amin Ansari, Josep Torrellas:
Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules. HPCA 2014: 84-95 - [c138]Shanxiang Qi, Abdullah Muzahid, Wonsun Ahn, Josep Torrellas:
Dynamically detecting and tolerating IF-Condition Data Races. HPCA 2014: 120-131 - [c137]Amin Ansari, Asit K. Mishra, Jianping Xu, Josep Torrellas:
Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks. HPCA 2014: 440-451 - [c136]Xuehai Qian, Benjamín Sahelices, Josep Torrellas:
OmniOrder: Directory-based conflict serialization of transactions. ISCA 2014: 421-432 - [c135]Nima Honarmand, Josep Torrellas:
Replay debugging: Leveraging record and replay for program debugging. ISCA 2014: 445-456 - [c134]Wonsun Ahn, Jiho Choi, Thomas Shull, María Jesús Garzarán, Josep Torrellas:
Improving JavaScript performance by deconstructing the type system. PLDI 2014: 496-507 - [c133]Ehsan Totoni, Josep Torrellas, Laxmikant V. Kalé:
Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy. SC 2014: 1047-1058 - [e3]José Nelson Amaral, Josep Torrellas:
International Conference on Parallel Architectures and Compilation, PACT '14, Edmonton, AB, Canada, August 24-27, 2014. ACM 2014, ISBN 978-1-4503-2809-8 [contents] - 2013
- [j30]Ulya R. Karpuzcu, Nam Sung Kim, Josep Torrellas:
Coping with Parametric Variation at Near-Threshold Voltages. IEEE Micro 33(4): 6-14 (2013) - [c132]Josep Torrellas:
Extreme scale computer architecture: Energy efficiency from the ground up. ASAP 2013: 1 - [c131]Wonsun Ahn, Yuelu Duan, Josep Torrellas:
DeAliaser: alias speculation using atomic region support. ASPLOS 2013: 167-180 - [c130]Nima Honarmand, Nathan Dautenhahn, Josep Torrellas, Samuel T. King, Gilles Pokam, Cristiano Pereira:
Cyrus: unintrusive application-level record-replay for replay parallelism. ASPLOS 2013: 193-206 - [c129]Xuehai Qian, Josep Torrellas, Benjamín Sahelices, Depei Qian:
Volition: scalable and precise sequential consistency violation detection. ASPLOS 2013: 535-548 - [c128]Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua B. Fryman, Ivan Ganev, Roger A. Golliver, Rob C. Knauerhase, Richard Lethin, Benoît Meister, Asit K. Mishra, Wilfred R. Pinfold, Justin Teller, Josep Torrellas, Nicolas Vasilache, Ganesh Venkatesh, Jianping Xu:
Runnemede: An architecture for Ubiquitous High-Performance Computing. HPCA 2013: 198-209 - [c127]Aditya Agrawal, Prabhat Jain, Amin Ansari, Josep Torrellas:
Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. HPCA 2013: 400-411 - [c126]Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke:
Illusionist: Transforming lightweight cores into aggressive cores on demand. HPCA 2013: 436-447 - [c125]Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas:
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. HPCA 2013: 542-553 - [c124]Yuelu Duan, Abdullah Muzahid, Josep Torrellas:
WeeFence: toward making fences free in TSO. ISCA 2013: 213-224 - [c123]Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Emile Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas:
QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs. ISCA 2013: 643-654 - [c122]Xuehai Qian, Josep Torrellas, Benjamín Sahelices, Depei Qian:
BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment. MICRO 2013: 371-382 - 2012
- [j29]Josep Torrellas:
2012 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro 32(5): 4-5 (2012) - [c121]Ulya R. Karpuzcu, Krishna B. Kolluru, Nam Sung Kim, Josep Torrellas:
VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. DSN 2012: 1-11 - [c120]Xuehai Qian, Benjamín Sahelices, Josep Torrellas:
BulkSMT: Designing SMT processors for atomic-block execution. HPCA 2012: 153-164 - [c119]Shanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas:
Pacman: Tolerating asymmetric data races with unintrusive hardware. HPCA 2012: 349-360 - [c118]Yuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas:
BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocks. HPCA 2012: 361-372 - [c117]Josep Torrellas:
FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper. ICCD 2012: 3-4 - [c116]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Pratap Pattnaik, Josep Torrellas:
FlexRAM: Toward an advanced Intelligent Memory system. ICCD 2012: 5-14 - [c115]Ehsan Totoni, Babak Behzad, Swapnil Ghike, Josep Torrellas:
Comparing the power and performance of Intel's SCC to state-of-the-art CPUs and GPUs. ISPASS 2012: 78-87 - [c114]Abdullah Muzahid, Shanxiang Qi, Josep Torrellas:
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically. MICRO 2012: 363-375 - 2011
- [c113]Rishi Agarwal, Josep Torrellas:
FlexBulk: intelligently forming atomic blocks in blocked-execution multiprocessors to minimize squashes. ISCA 2011: 33-44 - [c112]Rishi Agarwal, Pranav Garg, Josep Torrellas:
Rebound: scalable checkpointing for coherent shared memory. ISCA 2011: 153-164 - [r2]Josep Torrellas:
Cache-Only Memory Architecture (COMA). Encyclopedia of Parallel Computing 2011: 216-220 - [r1]Josep Torrellas:
Speculation, Thread-Level. Encyclopedia of Parallel Computing 2011: 1894-1900 - 2010
- [c111]Brian Greskamp, Ulya R. Karpuzcu, Josep Torrellas:
LeadOut: Composing low-overhead frequency-enhancing techniques for single-thread performance in configurable multicores. HPCA 2010: 1-12 - [c110]Josep Torrellas, Bill Gropp, Vivek Sarkar, Jaime H. Moreno, Kunle Olukotun:
Extreme scale computing: Challenges and opportunities. HPCA 2010: 1 - [c109]Adrian Nistor, Darko Marinov, Josep Torrellas:
InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing. MICRO 2010: 251-262 - [c108]Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas:
AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection. MICRO 2010: 287-297 - [c107]Xuehai Qian, Wonsun Ahn, Josep Torrellas:
ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment. MICRO 2010: 447-458 - [c106]Josep Torrellas, Bill Gropp, Jaime H. Moreno, Kunle Olukotun, Vivek Sarkar:
Extreme scale computing: challenges and opportunities. PPoPP 2010: 101-102
2000 – 2009
- 2009
- [j28]Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, Josep Torrellas:
Two hardware-based approaches for deterministic multiprocessor replay. Commun. ACM 52(6): 93-100 (2009) - [j27]Josep Torrellas, Luis Ceze, James Tuck, Calin Cascaval, Pablo Montesinos, Wonsun Ahn, Milos Prvulovic:
The Bulk Multicore architecture for improved programmability. Commun. ACM 52(12): 58-65 (2009) - [j26]Josep Torrellas:
Architectures for Extreme-Scale Computing. Computer 42(11): 28-35 (2009) - [j25]James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze:
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro 29(1): 84-95 (2009) - [c105]Pablo Montesinos, Matthew Hicks, Samuel T. King, Josep Torrellas:
Capo: a software-hardware interface for practical deterministic multiprocessor replay. ASPLOS 2009: 73-84 - [c104]Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig B. Zilles:
Blueshift: Designing processors for timing speculation from the ground up. HPCA 2009: 213-224 - [c103]Josep Torrellas:
How to build a useful thousand-core manycore system? IPDPS 2009: 1 - [c102]Abdullah Muzahid, Darío Suárez Gracia, Shanxiang Qi, Josep Torrellas:
SigRace: signature-based data race detection. ISCA 2009: 337-348 - [c101]Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong:
BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support. MICRO 2009: 133-144 - [c100]Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas:
The BubbleWrap many-core: popping cores for sequential acceleration. MICRO 2009: 447-458 - [c99]Adrian Nistor, Darko Marinov, Josep Torrellas:
Light64: lightweight hardware support for data race detection during systematic testing of parallel programs. MICRO 2009: 541-552 - 2008
- [c98]Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos, Josep Torrellas:
Concurrency control with data coloring. MSPC 2008: 6-10 - [c97]James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas:
SoftSig: software-exposed hardware signatures for code analysis and optimization. ASPLOS 2008: 145-156 - [c96]Pablo Montesinos, Luis Ceze, Josep Torrellas:
DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Effciently. ISCA 2008: 289-300 - [c95]Radu Teodorescu, Josep Torrellas:
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. ISCA 2008: 363-374 - [c94]Abhishek Tiwari, Josep Torrellas:
Facelift: Hiding and slowing down aging in multicores. MICRO 2008: 129-140 - [c93]Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas:
EVAL: Utilizing processors with variation-induced timing errors. MICRO 2008: 423-434 - 2007
- [j24]Smruti R. Sarangi, Satish Narayanasamy, Bruce Carneal, Abhishek Tiwari, Brad Calder, Josep Torrellas:
Patching Processor Design Errors with Programmable Hardware. IEEE Micro 27(1): 12-25 (2007) - [c92]Brian Greskamp, Josep Torrellas:
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. PACT 2007: 213-224 - [c91]Pablo Montesinos, Wei Liu, Josep Torrellas:
Using Register Lifetime Predictions to Protect Register Files against Soft Errors. DSN 2007: 286-296 - [c90]Luis Ceze, Pablo Montesinos, Christoph von Praun, Josep Torrellas:
Colorama: Architectural Support for Data-Centric Synchronization. HPCA 2007: 133-144 - [c89]James Tuck, Wei Liu, Josep Torrellas:
CAP: Criticality analysis for power-efficient speculative multithreading. ICCD 2007: 409-416 - [c88]Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas:
BulkSC: bulk enforcement of sequential consistency. ISCA 2007: 278-289 - [c87]Abhishek Tiwari, Smruti R. Sarangi, Josep Torrellas:
ReCycle: : pipeline adaptation to tolerate process variation. ISCA 2007: 323-334 - [c86]Brian Greskamp, Smruti R. Sarangi, Josep Torrellas:
Threshold Voltage Variation Effects on Aging-Related Hard Failure Rates. ISCAS 2007: 1261-1264 - [c85]Smruti R. Sarangi, Brian Greskamp, Josep Torrellas:
A Model for Timing Errors in Processors with Parameter Variation. ISQED 2007: 647-654 - [c84]Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas:
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. MICRO 2007: 27-42 - [c83]Karin Strauss, Xiaowei Shen, Josep Torrellas:
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. MICRO 2007: 327-342 - [c82]Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau:
Estimating design time for system circuits. VLSI-SoC 2007: 60-65 - 2006
- [j23]Josep Torrellas:
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 26(1): 8-9 (2006) - [j22]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Energy-Efficient Thread-Level Speculation. IEEE Micro 26(1): 80-91 (2006) - [j21]Radu Teodorescu, Jun Nakano, Josep Torrellas:
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. IEEE Micro 26(5): 28-40 (2006) - [j20]Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau:
CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. 3(2): 182-208 (2006) - [c81]Paul Sack, Brian E. Bliss, Zhiqiang Ma, Paul Petersen, Josep Torrellas:
Accurate and efficient filtering for the Intel thread checker race detector. ASID 2006: 34-41 - [c80]Smruti R. Sarangi, Brian Greskamp, Josep Torrellas:
CADRE: Cycle-Accurate Deterministic Replay for Hardware Debugging. DSN 2006: 301-312 - [c79]Jun Nakano, Pablo Montesinos, Kourosh Gharachorloo, Josep Torrellas:
ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers. HPCA 2006: 200-211 - [c78]Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval:
Bulk Disambiguation of Speculative Threads in Multiprocessors. ISCA 2006: 227-238 - [c77]Karin Strauss, Xiaowei Shen, Josep Torrellas:
Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors. ISCA 2006: 327-338 - [c76]Smruti R. Sarangi, Abhishek Tiwari, Josep Torrellas:
Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware. MICRO 2006: 26-37 - [c75]Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, Josep Torrellas:
PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection. MICRO 2006: 38-52 - [c74]James Tuck, Luis Ceze, Josep Torrellas:
Scalable Cache Miss Handling for High Memory-Level Parallelism. MICRO 2006: 409-422 - [c73]Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas:
POSH: a TLS compiler that exploits program structure. PPoPP 2006: 158-167 - [e2]Josep Torrellas:
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006. ACM 2006, ISBN 1-59593-576-2 [contents] - [e1]Josep Torrellas, Siddhartha Chatterjee:
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2006, New York, New York, USA, March 29-31, 2006. ACM 2006, ISBN 1-59593-189-9 [contents] - 2005
- [j19]Yuanyuan Zhou, Pin Zhou, Feng Qin, Wei Liu, Josep Torrellas:
Efficient and flexible architectural support for dynamic monitoring. ACM Trans. Archit. Code Optim. 2(1): 3-33 (2005) - [j18]María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas:
Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. 2(3): 247-279 (2005) - [c72]Radu Teodorescu, Josep Torrellas:
Prototyping Architectural Support for Program Rollback Using FPGAs. FCCM 2005: 23-32 - [c71]Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas:
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS 2005: 179-188 - [c70]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient. ICS 2005: 219-228 - 2004
- [j17]Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas:
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. 3 (2004) - [j16]Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas:
iWatcher: Simple, General Architectural Support for Software Debugging. IEEE Micro 24(6): 50-56 (2004) - [c69]Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas:
iWatcher: Efficient Architectural Support for Software Debugging. ISCA 2004: 224-237 - [c68]Pin Zhou, Wei Liu, Long Fei, Shan Lu, Feng Qin, Yuanyuan Zhou, Samuel P. Midkiff, Josep Torrellas:
AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants. MICRO 2004: 269-280 - 2003
- [j15]José F. Martínez, Josep Torrellas:
Speculative Synchronization: Programmability and Performance for Parallel Codes. IEEE Micro 23(6): 126-134 (2003) - [j14]Yan Solihin, Jaejin Lee, Josep Torrellas:
Correlation Prefetching with a User-Level Memory Thread. IEEE Trans. Parallel Distributed Syst. 14(6): 563-580 (2003) - [c67]María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas:
Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT 2003: 170-181 - [c66]Anthony-Trung Nguyen, Josep Torrellas:
Design Trade-Offs in High-Throughput Coherence Controllers. IEEE PACT 2003: 194-205 - [c65]María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas:
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA 2003: 191-202 - [c64]Milos Prvulovic, Josep Torrellas:
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. ISCA 2003: 110-121 - [c63]Michael C. Huang, Jose Renau, Josep Torrellas:
Positional Adaptation of Processors: Application to Energy Reduction. ISCA 2003: 157-168 - [c62]Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas:
Programming the FlexRAM parallel intelligent memory system. PPoPP 2003: 49-60 - 2002
- [j13]Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas:
Software Trace Cache for Commercial Applications. Int. J. Parallel Program. 30(5): 373-395 (2002) - [c61]José F. Martínez, Josep Torrellas:
Speculative synchronization: applying thread-level speculation to explicitly parallel applications. ASPLOS 2002: 18-29 - [c60]Marcelo H. Cintra, Josep Torrellas:
Speculative Multithreading Eliminating Squashes through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors. HPCA 2002: 43-54 - [c59]Francis H. Dang, María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Alin Jula, Hao Yu, Nancy M. Amato, Lawrence Rauchwerger, Josep Torrellas:
SmartApps: An Application Centric Approach to High Performance Computing: Compiler-Assisted Software and Hardware Support for Reduction Operations. IPDPS 2002 - [c58]Milos Prvulovic, Josep Torrellas, Zheng Zhang:
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors. ISCA 2002: 111-122 - [c57]Yan Solihin, Josep Torrellas, Jaejin Lee:
Using a User-Level Memory Thread for Correlation Prefetching. ISCA 2002: 171-182 - [c56]Michael C. Huang, Jose Renau, Josep Torrellas:
Energy-efficient hybrid wakeup logic. ISLPED 2002: 196-201 - [c55]José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas:
Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO 2002: 3-14 - 2001
- [j12]Venkata Krishnan, Josep Torrellas:
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. Int. J. Parallel Program. 29(1): 3-33 (2001) - [j11]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism 3 (2001) - [j10]Yan Solihin, Jaejin Lee, Josep Torrellas:
Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Trans. Computers 50(11): 1248-1266 (2001) - [c54]María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger:
Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. IEEE PACT 2001: 243-254 - [c53]Jaejin Lee, Yan Solihin, Josep Torrellas:
Automatically Mapping Code on an Intelligent Memory Architecture. HPCA 2001: 121-132 - [c52]Milos Prvulovic, María Jesús Garzarán, Lawrence Rauchwerger, Josep Torrellas:
Removing architectural bottlenecks to the scalability of speculative parallelization. ISCA 2001: 204-215 - [c51]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
L1 data cache decomposition for energy efficiency. ISLPED 2001: 10-15 - 2000
- [c50]Josep Torrellas, Liuxi Yang, Anthony-Trung Nguyen:
Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration. HPCA 2000: 15-25 - [c49]Qiang Cao, Josep Torrellas, H. V. Jagadish:
Unified Fine-Granularity Buffering of Index and Data: Approach and Implementation. ICCD 2000: 175-186 - [c48]Yan Solihin, Jaejin Lee, Josep Torrellas:
Adaptively Mapping Code in an Intelligent Memory Architecture. Intelligent Memory Systems 2000: 71-84 - [c47]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems 2000: 152-159 - [c46]Marcelo H. Cintra, José F. Martínez, Josep Torrellas:
Architectural support for scalable speculative parallelization in shared-memory multiprocessors. ISCA 2000: 13-24 - [c45]Lawrence Rauchwerger, Nancy M. Amato, Josep Torrellas:
SmartApps: An Application Centric Approach to High Performance Computing. LCPC 2000: 82-96 - [c44]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
A framework for dynamic energy efficiency and temperature management. MICRO 2000: 202-213
1990 – 1999
- 1999
- [j9]Fredrik Dahlgren, Josep Torrellas:
Cache-Only Memory Architectures. Computer 32(6): 72-79 (1999) - [j8]Zheng Zhang, Marcelo H. Cintra, Josep Torrellas:
Excel-NUMA: Toward Programmability, Simplicity, and High Performance. IEEE Trans. Computers 48(2): 256-264 (1999) - [j7]Chun Xia, Josep Torrellas:
Comprehensive Hardware and Software Support for Operating Systems to Exploit. IEEE Trans. Computers 48(5): 494-505 (1999) - [j6]Venkata Krishnan, Josep Torrellas:
A Chip-Multiprocessor Architecture with Speculative Multithreading. IEEE Trans. Computers 48(9): 866-880 (1999) - [c43]Venkata Krishnan, Josep Torrellas:
The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors. IEEE PACT 1999: 24-33 - [c42]Ye Zhang, Lawrence Rauchwerger, Josep Torrellas:
Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. HPCA 1999: 135-139 - [c41]Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas:
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA 1999: 322 - [c40]Qiang Cao, Josep Torrellas, Pedro Trancoso, Josep Lluís Larriba-Pey, Bob Knighten, Youjip Won:
Detailed Characterization of a Quad Pentium Pro Server Running TPC-D. ICCD 1999: 108- - [c39]Yi Kang, Wei Huang, Seung-Moon Yoo, Diana Keen, Zhenzhou Ge, Vinh Vi Lam, Josep Torrellas, Pratap Pattnaik:
FlexRAM: Toward an Advanced Intelligent Memory System. ICCD 1999: 192-201 - [c38]Pedro Trancoso, Josep Torrellas:
Cache Optimization for Memory-Resident Decision Support Commercial Workloads. ICCD 1999: 546- - [c37]David A. Koufaty, Josep Torrellas:
Compiler Support for Data Forwarding in Scalable Shared-Memory Multiprocessors. ICPP 1999: 181-191 - [c36]Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas:
Optimization of Instruction Fetch for Decision Support Workloads. ICPP 1999: 238-245 - [c35]Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero:
Software trace cache. International Conference on Supercomputing 1999: 119-126 - [c34]José F. Martínez, Josep Torrellas, José Duato:
Improving the performance of bristled CC-NUMA systems using virtual channels and adaptivity. International Conference on Supercomputing 1999: 202-209 - [c33]Josep Torrellas:
Upcoming Architectural Advances in DSM Machines and Their Impact on Programmability. PP 1999 - [c32]Josep Torrellas, Yan Solihin, Vinh Vi Lam:
Scal-Tool: Pinpointing and Quantifying Scalability Bottlenecks in DSM Multiprocessors. SC 1999: 17 - 1998
- [j5]Josep Torrellas, Chun Xia, Russell L. Daigle:
Optimizing the Instruction Cache Performance of the Operating System. IEEE Trans. Computers 47(12): 1363-1381 (1998) - [c31]Venkata Krishnan, Josep Torrellas:
An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors. IEEE PACT 1998: 286-293 - [c30]Sujoy Basu, Josep Torrellas:
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma. HPCA 1998: 152-161 - [c29]Ye Zhang, Lawrence Rauchwerger, Josep Torrellas:
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors. HPCA 1998: 162-173 - [c28]Yi Kang, Josep Torrellas, Thomas S. Huang:
Use IRAM for Rasterization. ICIP (3) 1998: 1010-1013 - [c27]Yi Kang, Josep Torrellas, Thomas S. Huang:
An IRAM architecture for image analysis and pattern recognition. ICPR 1998: 1561-1564 - [c26]David A. Koufaty, Josep Torrellas:
Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. International Conference on Supercomputing 1998: 53-60 - [c25]Venkata Krishnan, Josep Torrellas:
Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. International Conference on Supercomputing 1998: 85-92 - [c24]Venkata Krishnan, Josep Torrellas:
A Clustered Approach to Multithreaded Processors. IPPS/SPDP 1998: 627-634 - [c23]Josep Torrellas:
Computer architecture education at the University of Illinois. WCAE@ISCA 1998: 1 - 1997
- [j4]Josep Torrellas, Zheng Zhang:
The Performance of the Cedar Multistage Switching Network. IEEE Trans. Parallel Distributed Syst. 8(4): 321-336 (1997) - [c22]Liuxi Yang, Josep Torrellas:
Speeding up the Memory Hierarchy in Flat COMA Multiprocessors. HPCA 1997: 4-13 - [c21]Pedro Trancoso, Josep Lluís Larriba-Pey, Zheng Zhang, Josep Torrellas:
The Memory Performance of DSS Commercial Workloads in Shared-Memory Multiprocessors. HPCA 1997: 250-260 - [c20]Zheng Zhang, Josep Torrellas:
Reducing Remote Conflict Misses: NUMA with Remote Cache versus COMA. HPCA 1997: 272-281 - 1996
- [j3]David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas:
Data Forwarding in Scalable Shared-Memory Multiprocessors. IEEE Trans. Parallel Distributed Syst. 7(12): 1250-1264 (1996) - [c19]Chun Xia, Josep Torrellas:
Improving the Data Cache Performance of Multiprocessor Operating Systems. HPCA 1996: 85-94 - [c18]Alain Raynaud, Zheng Zhang, Josep Torrellas:
Distance-Adaptive Update Protocols for Scalable Shared-Memory Multiprocessors. HPCA 1996: 323-334 - [c17]Anthony-Trung Nguyen, Maged M. Michael, Arun Sharma, Josep Torrellas:
The Augmint multiprocessor simulation toolkit for Intel x86 architectures. ICCD 1996: 486-490 - [c16]Pedro Trancoso, Josep Torrellas:
The Impact of Speeding up Critical Sections with Data Prefetching and Forwarding. ICPP, Vol. 3 1996: 79-86 - [c15]Liuxi Yang, Josep Torrellas:
Optimizing Primary Data Caches for Parallel Scientific Applications: The Pool Buffer Approach. International Conference on Supercomputing 1996: 141-148 - [c14]Chun Xia, Josep Torrellas:
Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses. ISCA 1996: 271-282 - [c13]Manuel P. Malumbres, José Duato, Josep Torrellas:
An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors. SPDP 1996: 186-189 - [c12]Josep Torrellas:
Computer architecture education at the University of Illinois: current status and some thoughts. WCAE@HPCA 1996: 2 - 1995
- [j2]Josep Torrellas, Andrew Tucker, Anoop Gupta:
Evaluating the Performance of Cache-Affinity Scheduling in Shared-Memory Multiprocessors. J. Parallel Distributed Comput. 24(2): 139-151 (1995) - [c11]Josep Torrellas, Chun Xia, Russell L. Daigle:
Optimizing Instruction Cache Performance for Operating System Intensive Workloads. HPCA 1995: 360-369 - [c10]David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas:
Data Forwarding in Scalable Shared-Memory Multiprocessors. International Conference on Supercomputing 1995: 255-264 - [c9]Zheng Zhang, Josep Torrellas:
Speeding Up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching. ISCA 1995: 188-199 - 1994
- [j1]Josep Torrellas, Monica S. Lam, John L. Hennessy:
False Sharing ans Spatial Locality in Multiprocessor Caches. IEEE Trans. Computers 43(6): 651-663 (1994) - [c8]Josep Torrellas, David A. Koufaty, David A. Padua:
Comparing the Performance of the DASH and CEDAR Multiprocessors. ICPP (2) 1994: 304-308 - [c7]Josep Torrellas, Zheng Zhang:
The performance of the Cedar multistage switching network. SC 1994: 265-274 - [c6]Ding-Kai Chen, Josep Torrellas, Pen-Chung Yew:
An efficient algorithm for the run-time parallelization of DOACROSS loops. SC 1994: 518-527 - 1993
- [c5]Josep Torrellas, Andrew Tucker, Anoop Gupta:
Benefits of Cache-Affinity Scheduling in Shared-Memory Multiprocessors: A Summary. SIGMETRICS 1993: 272-274 - 1992
- [c4]Josep Torrellas, Anoop Gupta, John L. Hennessy:
Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System. ASPLOS 1992: 162-174 - 1990
- [c3]Josep Torrellas, John L. Hennessy:
Estimating the Performance Advantages of Relaxing Consistency in a Shared Memory Multiprocessor. ICPP (1) 1990: 26-34 - [c2]Josep Torrellas, Monica S. Lam, John L. Hennessy:
Share Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates. ICPP (2) 1990: 266-270 - [c1]Josep Torrellas, John L. Hennessy, Thierry Weil:
Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared Memory Multiprocessor. SIGMETRICS 1990: 163-172
Coauthor Index
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