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ORCIDJose Renau
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- affiliation: University of California, Santa Cruz, CA, USA
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2020 – today
- 2023
[c48]Sheng-Hong Wang, Hunter James Coffman, Kenneth Mayer, Sakshi Garg, Jose Renau
:
A Multi-threaded Fast Hardware Compiler for HDLs. CC 2023: 25-36- 2021
- [c47]David R. Ditzel, Roger Espasa, Nivard Aymerich, Allen Baum, Tom Berg, Jim Burr, Eric Hao, Jayesh Iyer, Miquel Izquierdo, Shankar Jayaratnam, Darren Jones, Chris Klingner, Jin Kim, Stephen Lee, Marc Lupon, Grigorios Magklis, Bojan Maric, Rajib Nath, Mike Neilly, J. Duane Northcutt, Bill Orner, Jose Renau, Gerard Reves, Xavier Reves, Tom Riordan, Pedro Sanchez, Sridhar Samudrala, Guillem Sole, Raymond Tang, Tommy Thorn, Francisco Torres, Sebastia Tortella, Daniel Yau:
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip. HCS 2021: 1-23 - [c46]Nursultan Kabylkas, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau:
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO 2021: 667-678 - 2020
- [j12]Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau:
LiveHD: A Productive Live Hardware Development Flow. IEEE Micro 40(4): 67-75 (2020) - [c45]Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau:
LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS 2020: 126-135 - [i1]Akash Sridhar, Nursultan Kabylkas, Jose Renau:
Load Driven Branch Predictor (LDBP). CoRR abs/2009.09064 (2020)
2010 – 2019
- 2019
- [c44]Rafael Trapani Possignolo, Jose Renau:
SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC 2019: 75 - [c43]Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau:
EMI Architectural Model and Core Hopping. MICRO 2019: 899-910 - 2018
- [j11]Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau:
GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1713-1726 (2018) - [p1]Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau:
Automated Pipeline Transformations with Fluid Pipelines. Advanced Logic Synthesis 2018: 125-150 - 2017
- [c42]Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an Interactive Synthesis Flow. DAC 2017: 74:1-74:6 - [c41]Elnaz Ebrahimi, Matthew R. Guthaus, Jose Renau:
Timing speculative SRAM. ISCAS 2017: 1-4 - [c40]Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau:
Level shifter design for voltage stacking. ISCAS 2017: 1-4 - [c39]Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau:
Liam: an actor based programming model for HDLs. MEMOCODE 2017: 185-188 - [c38]Daphne I. Gorman, Matthew R. Guthaus, Jose Renau:
Architectural opportunities for novel dynamic EMI shifting (DEMIS). MICRO 2017: 774-785 - 2016
- [j10]Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau:
Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. 12(4): 43:1-43:26 (2016) - [c37]Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium 2016: 1 - [c36]Sina Hassani, Gabriel Southern, Jose Renau:
LiveSim: Going live with microarchitecture simulation. HPCA 2016: 606-617 - [c35]Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau:
Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD 2016: 233-240 - [c34]Gabriel Southern, Jose Renau:
Overhead of deoptimization checks in the V8 javascript engine. IISWC 2016: 75-84 - [c33]Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau:
SRAM voltage stacking. ISCAS 2016: 1634-1637 - [c32]Gabriel Southern, Jose Renau:
Analysis of PARSEC workload scalability. ISPASS 2016: 133-142 - 2015
- [j9]Madan Mohan Das, Gabriel Southern, Jose Renau:
Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication. ACM Trans. Archit. Code Optim. 12(2): 23:23:1-23:23:26 (2015) - [c31]Jose Renau:
Message from the program chair. ISPASS 2015: vii - [c30]Madan Mohan Das, Gabriel Southern, Jose Renau:
Section based program analysis to reduce overhead of detecting unsynchronized thread communication. PPoPP 2015: 283-284 - 2014
- [j8]Amirkoushyar Ziabari, Je-Hyoung Park, Ehsan K. Ardestani, Jose Renau, Sung-Mo Kang, Ali Shakouri:
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2366-2379 (2014) - 2013
- [j7]Ehsan K. Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, Jose Renau:
Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1187-1200 (2013) - [c29]Ehsan K. Ardestani, Gabriel Southern, Jason Doung, Elnaz Ebrahimi, Jose Renau:
ESESC: A fast performance, power, and temperature multicore simulator. Hot Chips Symposium 2013: 1 - [c28]Ehsan K. Ardestani, Jose Renau:
ESESC: A fast multicore simulator using Time-Based Sampling. HPCA 2013: 448-459 - [c27]Alamelu Sankaranarayanan, Ehsan K. Ardestani, José Luis Briz, Jose Renau:
An energy efficient GPGPU memory hierarchy with tiny incoherent caches. ISLPED 2013: 9-14 - 2012
- [c26]Ehsan K. Ardestani, Elnaz Ebrahimi, Gabriel Southern, Jose Renau:
Thermal-aware sampling in architectural simulation. ISLPED 2012: 33-38 - 2011
- [j6]Jose Renau, Will Eatherton:
Hot Chips 22. IEEE Micro 31(2): 4-5 (2011) - [j5]Michael Brown, Jose Renau:
ReRack: power simulation for data centers with renewable energy generation. SIGMETRICS Perform. Evaluation Rev. 39(3): 77-81 (2011) - [c25]Sangeetha Sudhakrishnan, Rigo Dicochea, Jose Renau:
Releasing efficient beta cores to market early. ISCA 2011: 213-222 - [c24]Sangeetha Sudhakrishnan, Francisco J. Mesa-Martinez, Jose Renau:
A design time simulator for computer architects. ISQED 2011: 164-173 - 2010
- [c23]Francisco J. Mesa-Martinez, Ehsan K. Ardestani, Jose Renau:
Characterizing processor thermal behavior. ASPLOS 2010: 193-204
2000 – 2009
- 2009
- [c22]Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau:
Measuring and modeling variabilityusing low-cost FPGAs. FPGA 2009: 286 - [c21]Joseph Nayfach-Battilana, Jose Renau:
SOI, interconnect, package, and mainboard thermal characterization. ISLPED 2009: 327-330 - 2008
- [c20]Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau:
Measuring power and temperature from real processors. IPDPS 2008: 1-5 - [c19]Sangeetha Sudhakrishnan, Liying Su, Jose Renau:
Processor Verification with hwBugHunt. ISQED 2008: 224-229 - [c18]Sangeetha Sudhakrishnan, Janaki T. Madhavan, E. James Whitehead Jr., Jose Renau:
Understanding bug fix patterns in verilog. MSR 2008: 39-42 - 2007
- [c17]Francisco J. Mesa-Martinez, Michael Brown, Joseph Nayfach-Battilana, Jose Renau:
Measuring performance, power, and temperature from real processors. Experimental Computer Science 2007: 16 - [c16]Francisco J. Mesa-Martinez, Joseph Nayfach-Battilana, Jose Renau:
Power model validation through thermal measurements. ISCA 2007: 302-311 - [c15]Francisco J. Mesa-Martinez, Jose Renau:
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. MICRO 2007: 236-248 - [c14]Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau:
System and Procesor Design Effort Estimation. VLSI-SoC (Selected Papers) 2007: 1-21 - [c13]Cyrus Bazeghi, Francisco J. Mesa-Martinez, Brian Greskamp, Josep Torrellas, Jose Renau:
Estimating design time for system circuits. VLSI-SoC 2007: 60-65 - 2006
- [j4]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Energy-Efficient Thread-Level Speculation. IEEE Micro 26(1): 80-91 (2006) - [j3]Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau:
CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. 3(2): 182-208 (2006) - [c12]Francisco J. Mesa-Martinez, Michael C. Huang, Jose Renau:
SEED: scalable, efficient enforcement of dependences. PACT 2006: 254-264 - [c11]Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas:
POSH: a TLS compiler that exploits program structure. PPoPP 2006: 158-167 - 2005
- [c10]Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas:
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS 2005: 179-188 - [c9]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient. ICS 2005: 219-228 - [c8]Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau:
uComplexity: Estimating Processor Design Effort. MICRO 2005: 209-218 - 2004
- [b1]Jose Renau:
Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency. University of Illinois Urbana-Champaign, USA, 2004 - [j2]Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas:
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. 3 (2004) - 2003
- [c7]Michael C. Huang, Jose Renau, Josep Torrellas:
Positional Adaptation of Processors: Application to Energy Reduction. ISCA 2003: 157-168 - [c6]Basilio B. Fraguela, Jose Renau, Paul Feautrier, David A. Padua, Josep Torrellas:
Programming the FlexRAM parallel intelligent memory system. PPoPP 2003: 49-60 - 2002
- [c5]Michael C. Huang, Jose Renau, Josep Torrellas:
Energy-efficient hybrid wakeup logic. ISLPED 2002: 196-201 - [c4]José F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas:
Cherry: checkpointed early resource recycling in out-of-order microprocessors. MICRO 2002: 3-14 - 2001
- [j1]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. J. Instr. Level Parallelism 3 (2001) - [c3]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
L1 data cache decomposition for energy efficiency. ISLPED 2001: 10-15 - 2000
- [c2]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. Intelligent Memory Systems 2000: 152-159 - [c1]Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
A framework for dynamic energy efficiency and temperature management. MICRO 2000: 202-213
Coauthor Index
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