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ORCIDAbhishek A. Sinkar
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2010 – 2019
- 2016
[c15]Hadi Asghari Moghaddam
, Hamid Reza Ghasemi, Abhishek Arvind Sinkar, Indrani Paul, Nam Sung Kim:
VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency. DAC 2016: 151:1-151:6- 2014
- [j3]Abhishek A. Sinkar, Hamid Reza Ghasemi, Michael J. Schulte, Ulya R. Karpuzcu, Nam Sung Kim:
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 747-758 (2014) - [c14]Hoyoung Kim, Soojung Ryu, Abhishek A. Sinkar, Nam Sung Kim:
Quantitative comparison of the power reduction techniques for samsung reconfigurable processor. ISCAS 2014: 1736-1739 - [c13]Abhishek A. Sinkar, Hao Wang, Nam Sung Kim:
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores. ISQED 2014: 633-638 - 2013
- [j2]Abhishek A. Sinkar, Taejoon Park, Nam Sung Kim:
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 580-584 (2013) - [c12]Ulya R. Karpuzcu, Abhishek A. Sinkar, Nam Sung Kim, Josep Torrellas:
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing. HPCA 2013: 542-553 - [c11]Hao Wang, Abhishek A. Sinkar, Nam Sung Kim:
Improving platform energy: chip area trade-off in near-threshold computing environment. ICCAD 2013: 318-325 - 2012
- [j1]Nam Sung Kim, Abhishek A. Sinkar, Jun Seomun, Youngsoo Shin:
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1885-1890 (2012) - [c10]Hamid Reza Ghasemi, Abhishek A. Sinkar, Michael J. Schulte, Nam Sung Kim:
Cost-effective power delivery to support per-core voltage domains for power-constrained processors. DAC 2012: 56-61 - [c9]Abhishek A. Sinkar, Hao Wang, Nam Sung Kim:
Workload-aware voltage regulator optimization for power efficient multi-core processors. DATE 2012: 1134-1137 - 2011
- [c8]Abhishek A. Sinkar, Nam Sung Kim:
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. ASP-DAC 2011: 725-730 - 2010
- [c7]Abhishek A. Sinkar, Nam Sung Kim:
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits. ISQED 2010: 791-796 - [c6]Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti:
Combating Aging with the Colt Duty Cycle Equalizer. MICRO 2010: 103-114
2000 – 2009
- 2009
- [c5]Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim:
Statistical static timing analysis considering leakage variability in power gated designs. ISLPED 2009: 57-62 - [c4]Nam Sung Kim, Jun Seomun, Abhishek A. Sinkar, Jungseob Lee, Tae Hee Han, Ken Choi, Youngsoo Shin:
Frequency and yield optimization using power gates in power-constrained designs. ISLPED 2009: 121-126 - [c3]Abhishek A. Sinkar, Nam Sung Kim:
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. ISLPED 2009: 189-194 - [c2]Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar:
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. VLSI Design 2009: 479-484 - [c1]Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar:
False Path Aware Timing Yield Estimation under Variability. VTS 2009: 161-166
Coauthor Index
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