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2020 – today
- 2024
[c60]Frederik Kautz, Sven Gesper, Gia Bao Thieu, Hans-Martin Blüthgen, Holger Blume, Guillermo Payá Vayá:
Multi-Level Prototyping of a Vertical Vector AI Processing System. ASAP 2024: 1-2- [c59]Fabian Stuckmann, Guillermo Payá Vayá:
A Graph Neural Network Approach to Improve List Scheduling Heuristics Under Register-Pressure. MOCAST 2024: 1-6 - [c58]Moritz Weißbrich, Alexander Meyer, Adilet Dossanov, Vadim Issakov, Guillermo Payá Vayá:
A 505nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs. NorCAS 2024: 1-6 - 2023
- [j14]Luciano S. Martínez Rau
, Moritz Weißbrich, Guillermo Payá Vayá:
A 4μW Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle. J. Signal Process. Syst. 95(4): 407-424 (2023) - [c57]Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Marc Reichenbach:
TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. ARC 2023: 307-321 - [c56]Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá:
Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology. ARC 2023: 357-360 - [c55]Michael Beyer, Sven Gesper, Andre Guntoro, Guillermo Payá Vayá, Holger Blume:
Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency. ASAP 2023: 61-68 - [c54]Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer:
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE 2023: 1-6 - [c53]Sven Gesper, Gia Bao Thieu, Daniel Köhler, Markus Kock, Tim Berthold, Oliver Renke, Holger Blume, Guillermo Payá Vayá:
N2V2PRO: Neural Network Mapping Framework for a Custom Vector Processor Architecture. ICCE-Berlin 2023: 94-99 - [c52]Sven Gesper, Fabian Stuckmann, Lucy Wöbbekind, Guillermo Payá Vayá:
PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations. SAMOS 2023: 225-240 - 2022
- [j13]Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
A Survey on Application Specific Processor Architectures for Digital Hearing Aids. J. Signal Process. Syst. 94(11): 1293-1308 (2022) - [c51]Moritz Weißbrich, Holger Blume, Guillermo Payá Vayá:
A Silicon-Proof Controller System for Flexible Ultra-Low-Power Energy Harvesting Platforms. MOCAST 2022: 1-6 - [c50]Moritz Weißbrich, Guillermo Payá Vayá:
NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers. SAMOS 2022: 103-119 - 2021
- [j12]Sven Gesper, Moritz Weißbrich, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá Vayá:
Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. Int. J. Parallel Program. 49(4): 541-569 (2021) - [c49]Fabian Stuckmann, Pasha A. Fistanto, Guillermo Payá Vayá:
PATARA: A REVERSI-Based Open-Source Tool for Post-Silicon Validation of Processor Cores. MOCAST 2021: 1-6 - [c48]Moritz Weißbrich, Javier Andrés Moreno-Medina, Guillermo Payá Vayá:
Using Genetic Algorithms to Optimize the Instruction-Set Encoding on Processor Cores. MOCAST 2021: 1-6 - 2020
- [j11]Florian Giesemann, Lukas Gerlach, Guillermo Payá Vayá:
Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers. J. Signal Process. Syst. 92(7): 655-678 (2020) - [c47]Marc-Nils Wahalla, Guillermo Payá Vayá, Holger Blume:
CereBridge: An Efficient, FPGA-based Real-Time Processing Platform for True Mobile Brain-Computer Interfaces. EMBC 2020: 4046-4050 - [c46]Lukas Gerlach, Fabian Stuckmann, Holger Blume, Guillermo Payá Vayá:
Issue-Slot Based Predication Encoding Technique for VLIW Processors. MOCAST 2020: 1-6 - [c45]Jens Karrenbauer, Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
Design Space Exploration Framework for Tensilica-Based Digital Audio Processors in Hearing Aids. MOCAST 2020: 1-6 - [c44]Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá Vayá:
A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures. MOCAST 2020: 1-6
2010 – 2019
- 2019
- [j10]Moritz Weißbrich, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá Vayá:
FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. Integr. 69: 120-137 (2019) - [j9]Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer:
Dynamic self-reconfiguration of a MIPS-based soft-core processor architecture. J. Parallel Distributed Comput. 133: 391-406 (2019) - [j8]Nico Mentzer, Jannik Mahr, Guillermo Payá Vayá, Holger Blume:
Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction. J. Syst. Archit. 97: 335-348 (2019) - [j7]Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá Vayá:
Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction. J. Syst. Archit. 100 (2019) - [j6]Angel Mario Castro Martinez, Lukas Gerlach, Guillermo Payá Vayá, Hynek Hermansky, Jasper Ooster, Bernd T. Meyer:
DNN-based performance measures for predicting error rates in automatic speech recognition and optimizing hearing aid parameters. Speech Commun. 106: 44-56 (2019) - [c43]Amir Najafi, Lennart Bamberg, Guillermo Payá Vayá, Alberto García Ortiz:
A Coding Approach to Improve the Energy Efficiency of Approximate NoCs. ReCoSoC 2019: 74-81 - [c42]Sven Gesper, Moritz Weißbrich, Stephan Nolting, Tobias Stuckenberg, Pekka Jääskeläinen, Holger Blume, Guillermo Payá Vayá:
Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. SAMOS 2019: 3-17 - [c41]Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
KAVUAKA: A Low Power Application Specific Hearing Aid Processor. VLSI-SoC 2019: 99-104 - 2018
- [j5]Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz:
Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(4): 736-745 (2018) - [c40]Christian Dietrich, Achim Schmider, Oskar Pusz, Guillermo Payá Vayá, Daniel Lohmann:
Cross-layer fault-space pruning for hardware-assisted fault injection. DAC 2018: 79:1-79:6 - [c39]Pekka Jääskeläinen, Aleksi Tervo, Guillermo Payá Vayá, Timo Viitanen, Nicolai Behmann, Jarmo Takala, Holger Blume:
Transport-Triggered Soft Cores. IPDPS Workshops 2018: 83-90 - 2017
- [j4]Guillermo Payá Vayá, Andreas Gerstlauer:
Guest Editorial: Special Issue on the 2015 International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (SAMOS XV). Int. J. Parallel Program. 45(6): 1417-1419 (2017) - [j3]Guillermo Payá Vayá, Christopher Bartels, Holger Blume:
Small footprint synthesizable temperature sensor for FPGA devices. J. Syst. Archit. 76: 28-38 (2017) - [c38]Stephan Nolting, Florian Giesemann, Julian Hartig, Achim Schmider, Guillermo Payá Vayá:
Application-specific soft-core vector processor for advanced driver assistance systems. FPL 2017: 1-2 - [c37]Stephan Nolting, Lin Liu, Guillermo Payá Vayá:
Two-LUT-based synthesizable temperature sensor for Virtex-6 FPGA devices. FPL 2017: 1-4 - [c36]Julian Hartig, Guillermo Payá Vayá, Henrik Heymann, Holger Blume:
Tool-supported design space exploration of a processor system for SIFT-feature detection. ICCE-Berlin 2017: 168-169 - [c35]Christopher Seifert, Joachim Thiemann, Lukas Gerlach, Tobias Volkmar, Guillermo Payá Vayá, Holger Blume, Steven van de Par:
Real-time implementation of a GMM-based binaural localization algorithm on a VLIW-SIMD processor. ICME 2017: 145-150 - [c34]Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz:
A fair comparison of adders in stochastic regime. PATMOS 2017: 1-6 - [c33]Moritz Weißbrich, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz:
FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. PATMOS 2017: 1-8 - [c32]Julian Hartig, Guillermo Payá Vayá, Nico Mentzer, Holger Blume:
Balanced application-specific processor system for efficient SIFT-feature detection. SAMOS 2017: 78-87 - [c31]Lukas Gerlach, Guillermo Payá Vayá, Shuang Liu, Moritz Weißbrich, Holger Blume, Daniel Marquardt, Simon Doclo:
Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP. SAMOS 2017: 88-96 - [c30]Florian Giesemann, Guillermo Payá Vayá, Lukas Gerlach, Holger Blume, Fabian Pflug, Gabriele von Voigt:
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling. SAMOS 2017: 179-187 - 2016
- [j2]Nico Mentzer, Guillermo Payá Vayá, Holger Blume:
Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction. J. Signal Process. Syst. 85(1): 83-99 (2016) - [c29]Nicolai Behmann, Christopher Seifert, Guillermo Payá Vayá, Holger Blume, Pekka Jääskeläinen, Joonas Multanen, Heikki Kultala, Jarmo Takala, Joachim Thiemann, Steven van de Par:
Customized high performance low power processor for binaural speaker localization. ICECS 2016: 392-395 - [c28]Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume, Sebastian Niemann, Christian Müller-Schloer:
Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture. IPDPS Workshops 2016: 172-180 - [c27]Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. SiPS 2016: 254-259 - [c26]Bernd T. Meyer, Sri Harish Reddy Mallidi, Angel Mario Castro Martinez, Guillermo Payá Vayá, Hendrik Kayser, Hynek Hermansky:
Performance monitoring for automatic speech recognition in noisy multi-channel environments. SLT 2016: 50-56 - 2015
- [c25]Stephan Nolting, Guillermo Payá Vayá, Florian Giesemann, Holger Blume:
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture. ARC 2015: 401-410 - [c24]Christopher Bartels, Chao Zhang, Guillermo Payá Vayá, Holger Blume:
A Synthesizable Temperature Sensor on FPGA Using DSP-Slices for Reduced Calibration Overhead and Improved Stability. ARCS 2015: 161-172 - [c23]Rochus Nowosielski, Lukas Gerlach, Stephan Bieband, Guillermo Payá Vayá, Holger Blume:
FLINT: layout-oriented FPGA-based methodology for fault tolerant ASIC design. DATE 2015: 297-300 - [c22]Christopher Seifert, Guillermo Payá Vayá, Holger Blume, Tobias Herzke, Volker Hohmann:
A mobile SoC-based platform for evaluating hearing aid algorithms and architectures. ICCE-Berlin 2015: 93-97 - [c21]Daniel Pfefferkorn, Achim Schmider, Guillermo Payá Vayá, Martin Neuenhahn, Holger Blume:
FNOCEE: A framework for NoC evaluation by FPGA-based emulation. SAMOS 2015: 86-95 - [c20]Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
An area efficient real- and complex-valued multiply-accumulate SIMD unit for digital signal processors. SiPS 2015: 1-6 - 2014
- [c19]Michele Fenzi, Jörn Ostermann, Nico Mentzer, Guillermo Payá Vayá, Holger Blume, Tu Ngoc Nguyen, Thomas Risse:
ASEV - Automatic situation assessment for event-driven video analysis. AVSS 2014: 37-43 - [c18]Oliver Jakob Arndt, Daniel Becker, Florian Giesemann, Guillermo Payá Vayá, Christopher Bartels, Holger Blume:
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms. ICSAMOS 2014: 125-132 - [c17]Florian Giesemann, Guillermo Payá Vayá, Holger Blume, Matthias Limmer, Werner Ritter:
A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications. ICSAMOS 2014: 314-321 - [c16]Nico Mentzer, Guillermo Payá Vayá, Holger Blume, Nora von Egloffstein, Werner Ritter:
Instruction-set extension for an ASIP-based SIFT feature extraction. ICSAMOS 2014: 335-342 - [c15]Julian Hartig, Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
Customizing a VLIW-SIMD application-specific instruction-set processor for hearing aid devices. SiPS 2014: 115-120 - 2011
- [b1]Guillermo Payá Vayá:
Design and analysis of a generic VLIW processor for multimedia applications. University of Hanover, 2011, ISBN 978-3-8440-0064-1, pp. 1-177 - 2010
- [j1]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
A Multi-Shared Register File Structure for VLIW Processors. J. Signal Process. Syst. 58(2): 215-231 (2010) - [c14]Guillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch:
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures. ASAP 2010: 151-158
2000 – 2009
- 2009
- [c13]Guillermo Payá Vayá, Javier Martín-Langerwerf, Sören Moch, Peter Pirsch:
An Enhanced DMA Controller in SIMD Processors for Video Applications. ARCS 2009: 159-170 - [c12]Guillermo Payá Vayá, Javier Martín-Langerwerf, Florian Giesemann, Holger Blume, Peter Pirsch:
Instruction merging to increase parallelism in VLIW architectures. SoC 2009: 143-146 - 2007
- [c11]Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch:
Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler. ARCS 2007: 254-267 - [c10]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip. DSD 2007: 215-221 - [c9]Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch:
Design Space Exploration of Media Processors: A Parameterized Scheduler. ICSAMOS 2007: 41-49 - [c8]Guillermo Payá Vayá, Thomas Jambor, Konstantin Septinus, Sebastian Hesselbarth, Holger Flatt, Marc Freisfeld, Peter Pirsch:
ChipDesign: from theory to real world. WCAE 2007: 58-64 - 2005
- [c7]Guillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch:
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration. SAMOS 2005: 32-40 - 2004
- [c6]Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer:
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958 - [c5]Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá:
Architectures for ICT on FPGA. FPT 2004: 403-406 - [c4]Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá:
2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) 2004: 365-368 - 2003
- [c3]Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas:
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL 2003: 533-542 - [c2]Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá:
A new inverse discrete wavelet packet transform architecture. ISSPA (2) 2003: 443-446 - [c1]Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá:
Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) 2003: 121-128
Coauthor Index
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