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ORCIDRicardo José Colom-Palero
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2010 – 2019
- 2018
[j8]Rafael Gadea Gironés
, Ricardo José Colom-Palero, Vicente Herrero-Bosch:
Optimization of Deep Neural Networks Using SoCs with OpenCL. Sensors 18(5): 1384 (2018)
2000 – 2009
- 2009
- [c4]Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch:
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. ICSAMOS 2009: 1-8 - 2008
- [j7]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona:
A Mixed Hardware/Software SOFM Training System. Computación y Sistemas 11(4) (2008) - [j6]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero:
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. Microprocess. Microsystems 32(1): 33-44 (2008) - [c3]Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastiá, Fernando Mateo:
SoC-Based Implementation of the Backpropagation Algorithm for MLP. HIS 2008: 744-749 - 2007
- [j5]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona:
A wavelet-VQ system for real-time video compression. J. Real Time Image Process. 2(4): 271-280 (2007) - 2006
- [j4]Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero:
An active methodology for teaching electronic systems design. IEEE Trans. Educ. 49(3): 355-359 (2006) - [j3]Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés:
A Novel FPGA Architecture of a 2-D Wavelet Transform. J. VLSI Signal Process. 42(3): 273-284 (2006) - 2005
- [j2]Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés:
FPGA Implementation of a Pipelined On-Line Backpropagation. J. VLSI Signal Process. 40(2): 189-213 (2005) - 2004
- [j1]Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró:
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28(9): 509-518 (2004) - [c2]Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer:
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958 - 2003
- [c1]Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero:
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. FPL 2003: 1016-1019
Coauthor Index
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