"FPGA Implementation of a Pipelined On-Line Backpropagation."

Rafael Gadea Gironés et al. (2005)

> Home

Details and statistics

DOI: 10.1007/S11265-005-4961-3

access: closed

type: Journal Article

metadata version: 2020-05-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/GironesCCS05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/GironesCCS05
Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés:
FPGA Implementation of a Pipelined On-Line Backpropagation. J. VLSI Signal Process. 40(2): 189-213 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.