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ORCID27th VLSI-SoC 2019: Cuzco, Peru
- 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019. IEEE 2019, ISBN 978-1-7281-3915-9
- Gilles Jacquemod, Zhaopeng Wei, Yves Leduc, Emeric de Foucauld, Jérôme Prouvée, B. Blampey:
New design of analog and mixed-signal cells using back-gate cross-coupled structure. 21-26 - Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels:
A Distributed Body-Biasing Strategy for Asynchronous Circuits. 27-32 - Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza:
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. 34-39 - Kenneth Peter, Lars J. Svensson, Christoffer Fougstedt, Per Larsson-Edefors:
Hardware Considerations for Selection Networks. 40-45 - László Szilágyi, Jan Plíva, Ronny Henker, Frank Ellinger:
A Mixed-Signal Offset-Compensation System for Multi-Gbit/s Optical Receiver Frontends. 46-51 - Y. Serhan Gener
, Sezer Gören, H. Fatih Ugurdag:
Lossless Look-Up Table Compression for Hardware Implementation of Transcendental Functions. 52-57 - Hunter Nichols, Michael Grimes, Jennifer Sowash, Jesse Cirimelli-Low, Matthew R. Guthaus:
Automated Synthesis of Multi-Port Memories and Control. 59-64 - Qi Lu, Amir Masoud Gharehbaghi, Masahiro Fujita:
Approximate Arithmetic Circuit Design Using a Fast and Scalable Method. 65-70 - Keisuke Inoue:
An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. 71-74 - Michelangelo Grosso, Salvatore Rinaudo, Andrea Casalino, Matteo Sonza Reorda:
Software-Based Self-Test for Transition Faults: a Case Study. 76-81 - Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik:
Implementation-Independent Functional Test Generation for MSC Microprocessors. 82-87 - Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability. 88-93 - Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini:
A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI. 95-98 - Lukas Gerlach, Guillermo Payá Vayá, Holger Blume:
KAVUAKA: A Low Power Application Specific Hearing Aid Processor. 99-104 - Gerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas:
5G-and-Beyond Scalable Machines. 105-109 - Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik:
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. 111-116 - Atishay, Ankit Gupta, Rashmi Sonawat, Helik Kanti Thacker, Prasanth B:
SEARS: A Statistical Error and Redundancy Analysis Simulator. 117-122 - Vitor V. Bandeira, Felipe Rosa, Ricardo Augusto da Luz Reis, Luciano Ost:
Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis. 123-128 - Owais Talaat Waheed, Ibrahim Abe M. Elfadel:
Domain-Specific Architecture for IMU Array Data Fusion. 129-134 - Chen-Ying Hsieh, Ardalan Amiri Sani, Nikil D. Dutt:
SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures. 136-141 - Valentino Peluso, Matteo Grimaldi, Andrea Calimera:
Arbitrary-Precision Convolutional Neural Networks on Low-Power IoT Processors. 142-147 - Sandro Matheus V. N. Marques, Thiarles S. Medeiros, Fábio Diniz Rossi, Marcelo Caggiani Luizelli, Alessandro Gonçalves Girardi, Antonio Carlos Schneider Beck, Arthur Francisco Lorenzon:
The Impact of Turbo Frequency on the Energy, Performance, and Aging of Parallel Applications. 149-154 - Florian Protze, Martin Kreißig, Frank Ellinger, Sebastian Höppner, Stephan Hartmann, Stefan Hänzsche, Stefan Scholze, Georg Ellguth, Christian Mayr:
Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS. 155-158 - João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. 160-165 - Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles:
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture. 166-171 - Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. 172-177 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Evaluation of SET under Process Variability on FinFET Multi-level Design. 179-184 - Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen:
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. 185-190 - Soner Seçkiner, Longfei Wang, Selçuk Köse:
An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control. 191-196 - Solon Falas, Charalambos Konstantinou, Maria K. Michael:
A Hardware-based Framework for Secure Firmware Updates on Embedded Systems. 198-203 - Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda:
Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable. 204-209 - Arman Iranfar, Wellington Silva de Souza, Marina Zapater, Katzalin Olcoz, Samuel Xavier de Souza, David Atienza:
A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers. 211-216 - Robert Kirby, Saad Godil, Rajarshi Roy, Bryan Catanzaro:
CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks. 217-222 - F. L. Denis Nunes, Márcio Eduardo Kreutz:
Using SDN Strategies to Improve Resource Management On a NoC. 224-225 - Malek Souilem, Jai Narayan Tripathi, Wael Dghais, Belgacem Hamdi:
I/O Buffer Modelling for Power Supplies Noise Induced Jitter under Simultaneous Switching Outputs (SSO). 226-227 - Diego A. Silva, Orlando Verducci Jr., Duarte Lopes de Oliveira:
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. 228-229 - Wellington Silva de Souza, Arman Iranfar, Anderson B. N. da Silva, Marina Zapater, Samuel Xavier de Souza, Katzalin Olcoz, David Atienza:
A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers. 230-231 - Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, José L. Núñez-Yáñez, Samuel Xavier de Souza:
Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications. 232-233 - Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen:
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. 234-235 - Calebe Micael de Oliveira Conceição, Ricardo Augusto da Luz Reis:
Netlist Optimization by Gate Merging. 236-237 - Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis:
Probabilistic Models for Off-Line Arbiters in Embedded Systems. 238-239 - Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis:
Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs. 240-241 - Yu-Cheng Chen, Vincent John Mooney, Santiago Grijalva:
A Survey of Attack Models for Cyber-Physical Security Assessment in Electricity Grid. 242-243 - Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
A Digital Event-Based Strategy for ASK demodulation. 244-245 - Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis:
Robustness and Minimum Energy-Oriented FinFET Design. 247-248 - Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis:
Impact of Process Variability and Single Event Transient on FinFET Technology. 249-250 - Isadora Oliveira, Vitor V. Bandeira, Ricardo A. L. Reis, Luciano Ost:
Exploration of Techniques to Assess Soft Errors in Multicore Architectures. 251-252 - Vitor V. Bandeira, Isadora Oliveira, Felipe da Rosa, Ricardo A. L. Reis, Luciano Ost:
Soft Error Reliability Analysis of Autonomous Vehicles Software Stack. 253-254 - Atif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski:
Functional Verification of Hardware Dividers using Algebraic Model. 257-262 - Renato S. Feitoza, Manuel J. Barragán, Salvador Mir:
Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. 263-268 - Chenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC. 269-274 - Stavros Limnaios, Nicolas Sklavos, Odysseas G. Koufopavlou:
Lightweight Efficient Simeck32/64 Crypto-Core Designs and Implementations, for IoT Security. 275-280 - Adil Brik, Lioua Labrak, Laurent Carrel, Ian O'Connor, Ramy Iskander:
Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts. 281-286 - Rafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck:
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors. 287-292 - Ashfakh Ali, Sai Kiran, Arpan Jain, Zia Abbas:
A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications. 293-298 - Denis F. L. Nunes, Silvio Roberto Fernandes de Araujo, Márcio Eduardo Kreutz:
Optimizing an Architecture with Software Pipelining Strategies. 299-304 - Bin Wu, Matthew R. Guthaus:
Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization. 305-310 - Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez:
Exploiting Approximate Computing to Increase System Lifetime. 311-316 - Shahzad Muzaffar, Ibrahim Abe M. Elfadel:
Double Data Rate Dynamic Edge-Coded Signaling for Low-Power IoT Communication. 317-322 - Andrea Bocco, Tiago T. Jost, Albert Cohen, Florent de Dinechin, Yves Durand, Christian Fabre:
Byte-Aware Floating-point Operations through a UNUM Computing Unit. 323-328 - Kevin A. Cáceres Albinagorta, Calebe Conceição, Carlos Silva Cárdenas, Ricardo A. L. Reis:
Exploring area and total wirelength using a cell merging technique. 329-334 - Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin:
On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. 335-340 - Rafaella Elia, George Plastiras, Theocharis Theocharides:
Towards an Embedded and Real-Time Joint Human-Machine Monitoring Framework: Dataset optimization Techniques for Anomaly Detection. 341-346 - Diego V. Cirilo do Nascimento, Kyriakos Georgiou, Kerstin I. Eder, Samuel Xavier de Souza:
Exploiting guard band limits for energy gains in MPSoCs. 1-2
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