"Exploring Logic Gates Layout to Improve the Accuracy of Circuit ..."

Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen (2019)

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DOI: 10.1109/VLSI-SOC.2019.8920385

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen:
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. VLSI-SoC 2019: 234-235

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