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2020 – today
- 2024
[j149]Shiyan Yi
, Yudi Qiu, Lingfei Lu, Guohao Xu, Yong Gong, Xiaoyang Zeng, Yibo Fan:
GATe: Streamlining Memory Access and Communication to Accelerate Graph Attention Network With Near-Memory Processing. IEEE Comput. Archit. Lett. 23(1): 87-90 (2024)- [j148]Xiaoyang Zeng, Qizhen Zhu, Awais Ahmed, Muhammad Hanif, Mengshu Hou, Qiu Jie, Rui Xi, Syed Attique Shah:
Multi-granularity prior networks for uncertainty-informed patient-specific quality assurance. Comput. Biol. Medicine 179: 108925 (2024) - [j147]Yi Ling, Yujie Huang, Yujie Cai, Zhaojie Li, Mingyu Wang, Wenhong Li, Xiaoyang Zeng:
FSS: algorithm and neural network accelerator for style transfer. Sci. China Inf. Sci. 67(2) (2024) - [j146]Aorui Gou, Jingjing Liu, Xiaoxiang Chen, Xiaoyang Zeng, Yibo Fan:
CCTSS: The Combination of CNN and Transformer with Shared Sublayer for Detection and Classification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 141-156 (2024) - [j145]Zewei Ding, Qijuan Wu, Mingyu Wang, Jingjing Liu, Xiaoyang Zeng, Wenhong Li, Wei Huang, Zhi Liu, Xiao-Ping Zhang:
A Multimode Neuromorphic Vision Sensor With Improved Brightness Measurement Performance by Pulse Coding Method. IEEE Internet Things J. 11(4): 6266-6277 (2024) - [j144]Muhammad Hanif Tunio, Jian Ping Li, Xiaoyang Zeng, Faijan Akhtar, Syed Attique Shah, Awais Ahmed, Yu Yang, Md Belal Bin Heyat:
Meta-knowledge guided Bayesian optimization framework for robust crop yield estimation. J. King Saud Univ. Comput. Inf. Sci. 36(1): 101895 (2024) - [j143]Awais Ahmed, Xiaoyang Zeng, Rui Xi, Mengshu Hou, Syed Attique Shah:
MED-Prompt: A novel prompt engineering framework for medicine prediction on free-text clinical notes. J. King Saud Univ. Comput. Inf. Sci. 36(2): 101933 (2024) - [j142]Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen:
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits 59(7): 2248-2259 (2024) - [j141]Cong Tao, Liangbo Lei, Chaoyang Zheng, Yumei Huang, Zhiliang Hong, Xiaoyang Zeng:
A Low-Power, Compact, 0.1-5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR. IEEE J. Solid State Circuits 59(9): 2761-2773 (2024) - [j140]Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng:
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. IEEE J. Solid State Circuits 59(10): 3277-3289 (2024) - [j139]Mengjie Li, Haozhe Zhu, Siqi He, Hongyi Zhang, Jie Liao, Danfeng Zhai, Chixiao Chen, Qi Liu, Xiaoyang Zeng, Ninghui Sun, Ming Liu:
SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. IEEE J. Solid State Circuits 59(11): 3853-3865 (2024) - [j138]Chenyu Zhang, Yan Li, Wenfa Zhan, Wenping Geng, Ting Liang, Xiaoyang Zeng:
Examining the role of tap cell in suppressing single event transient effect in 28-nm CMOS technology. Microelectron. J. 143: 106055 (2024) - [j137]Jingjing Liu, Manlong Feng, Dongzhou Gu, Xiaoyang Zeng, Wanquan Liu, Xianchao Xiu:
Moving object detection in gigapixel-level videos using manifold sparse representation. Multim. Tools Appl. 83(6): 18381-18405 (2024) - [j136]Qi Zheng, Zhengzhong Tu, Pavan C. Madhusudana, Xiaoyang Zeng, Alan C. Bovik, Yibo Fan:
FAVER: Blind quality prediction of variable frame rate videos. Signal Process. Image Commun. 122: 117101 (2024) - [j135]Mengjie Li, Yujie Huang, Mingyu Wang, Wenhong Li, Xiaoyang Zeng:
STCC-Filter: A space-time-content correlation-based noise filter with self-adjusting threshold for event camera. Signal Process. Image Commun. 126: 117136 (2024) - [j134]Zhijian Hao, Heming Sun, Guohao Xu, Jiaming Liu, Xiankui Xiong, Xuanpeng Zhu, Xiaoyang Zeng, Yibo Fan:
Fast Transform Kernel Selection Based on Frequency Matching and Probability Model for AV1. IEEE Trans. Broadcast. 70(2): 693-707 (2024) - [j133]Lairong Fang, Shuwen Zhang, Yijie Li, Shunmin Wu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 107.6 dB-DR Three-Step Incremental ADC for Motion-Tolerate Biopotential Signals Recording. IEEE Trans. Biomed. Circuits Syst. 18(1): 111-122 (2024) - [j132]Yudi Qiu, Tao Huang, Yuxin Tang, Yanwei Liu, Yang Kong, Xulin Yu, Xiaoyang Zeng, Yibo Fan:
Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce Errors. IEEE Trans. Computers 73(3): 902-914 (2024) - [j131]Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han:
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 320-333 (2024) - [j130]Cong Tao, Jiangli Huang, Liangbo Lei, Yumei Huang, Zhiliang Hong, Xiaoyang Zeng:
A Compact 0.1-1.95 GHz, 1.5 dB NF LNTA Based on Cascode Inverters. IEEE Trans. Circuits Syst. II Express Briefs 71(2): 597-601 (2024) - [j129]Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng:
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1416-1420 (2024) - [j128]Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng:
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024) - [j127]Haozhe Zhu, Hongyi Zhang, Siqi He, Mengjie Li, Xiaoyang Zeng, Chixiao Chen:
Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2544-2548 (2024) - [j126]Yaoyi Chen, Yujie Huang, Mingyu Wang, Wenhong Li, Xiaoyang Zeng:
IMA-BLC: Iterative Median-Averaged Adaptive Black-Level Correction Method. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3598-3602 (2024) - [c232]Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng:
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC 2024: 551-556 - [c231]Chenlong He, Qi Zheng, Ruoxi Zhu, Xiaoyang Zeng, Yibo Fan, Zhengzhong Tu:
COVER: A Comprehensive Video Quality Evaluator. CVPR Workshops 2024: 5799-5809 - [c230]Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen:
ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. DATE 2024: 1-6 - [c229]Xi Cheng, Shu Cao, Shangmei Wang, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
A 1024-Neuron 1M-Synapse Event-Driven SNN Accelerator for DVS Applications. ISCAS 2024: 1-5 - [c228]Zewei Ding, Shangmei Wang, Yujie Cai, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
A Lossless Compression Algorithm with Hardware Implementation for Dynamic Vision Sensor. ISCAS 2024: 1-5 - [c227]Aorui Gou, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Privacy-preserving with Flexible Autoencoder for Video Coding for Machines. ISCAS 2024: 1-5 - [c226]Chenlong He, Wei Li, Xiaoxiang Chen, Zhijian Hao, Chao Liu, Xiaoyang Zeng, Yibo Fan:
CTU-Level Adaptive Quantization Method Joint with GOP based Temporal Filter for Video Coding. ISCAS 2024: 1-5 - [c225]Weiyan Li, Xianren Hao, Xiaguang Li, Yan Ma, Jingjing Liu, Huaxi Zhang, Xiaoyang Zeng, Zhiyuan Chen:
A Single-Stage Four-Phase Dual-Output Regulating Rectifier With Ultrafast Transient Response Using Double-Frequency Current-Wave Modulation. ISCAS 2024: 1-5 - [c224]Mengjie Li, Hongyi Zhang, Siqi He, Haozhe Zhu, Hao Zhang, Jinglei Liu, Jiayuan Chen, Zhenping Hu, Xiaoyang Zeng, Chixiao Chen:
A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. ISCAS 2024: 1-5 - [c223]Liyu Lin, Jingguo Wu, Xiaoyang Zeng, Yun Chen:
A Semi-Folded Based High-Power-Efficiency FFT for Frequency Offset Estimate. ISCAS 2024: 1-5 - [c222]Xinhao Mao, Ziyu Guo, Jun Han, Bo Hu, Xiaoyang Zeng:
Hardware Acceleration of Phase and Gain Control for Analog Beamforming. ISCAS 2024: 1-5 - [c221]Awais Ahmed, Mengshu Hou, Rui Xi, Xiaoyang Zeng, Syed Attique Shah:
Prompt-Eng: Healthcare Prompt Engineering: Revolutionizing Healthcare Applications with Precision Prompts. WWW (Companion Volume) 2024: 1329-1337 - 2023
- [j125]Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng:
Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(4): 986-999 (2023) - [j124]Tianxiang Qu, Qinjing Pan, Liheng Liu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred-Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction. IEEE J. Solid State Circuits 58(3): 796-805 (2023) - [j123]Aorui Gou, Heming Sun, Chao Liu, Xiaoyang Zeng, Yibo Fan:
A novel fast intra algorithm for VVC based on histogram of oriented gradient. J. Vis. Commun. Image Represent. 95: 103888 (2023) - [j122]Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Xiaoyong Xue, Xiaoyang Zeng:
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 364-377 (2023) - [j121]Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1639-1648 (2023) - [j120]Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng:
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4015-4027 (2023) - [j119]Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5242-5253 (2023) - [j118]Deyang Chen, Zhiwang Guo, Jinbei Fang, Chenyang Zhao, Jingwen Jiang, Keji Zhou, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng:
A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 276-280 (2023) - [j117]Hengyao Zhao, Chao Fan, Zhiyuan Chen, Pei Zheng, Xiaoyang Zeng, Zhiliang Hong:
A Tuning Range Extension Technique for Waveform-Shaping Single-Core CMOS Oscillators With No Dedicated Harmonic Tuning. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1306-1310 (2023) - [j116]Xunming Zhang, Long Liu, Di Wang, Ruijun Lin, Heyong Yang, Xiaoxin Xu, Jianguo Yang, Guozhong Xing, Xiaoyong Xue, Xiaoyang Zeng:
Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 2226-2230 (2023) - [j115]Zhiwang Guo, Deyang Chen, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Yixuan Liu, Haidong Tian, Xiankui Xiong, Keji Zhou, Xiaoyong Xue, Qi Liu, Xiaoyang Zeng:
An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2645-2649 (2023) - [j114]Xianwu Hu, Yu Wang, Zizhao Ma, Gan Wen, Zeming Wang, Zhichao Lu, Yunlong Liu, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4216-4220 (2023) - [j113]Zhijian Hao, Heming Sun, Sirui Li, Xiaoyang Zeng, Yibo Fan:
Area-Efficient Processing Elements-Based Adaptive Loop Filter Architecture With Optimized Memory for VVC. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4231-4235 (2023) - [j112]Yujie Huang, Wenshu Chen, Liyuan Peng, Yuhao Liu, Mingyu Wang, Xiao-Ping (Steven) Zhang, Xiaoyang Zeng:
LineDL: Processing Images Line-by-Line With Deep Learning. IEEE Trans. Image Process. 32: 3150-3162 (2023) - [j111]Wenshu Chen, Yujie Huang, Mingyu Wang, Xiaolin Wu, Xiaoyang Zeng:
TSDN: Two-Stage Raw Denoising in the Dark. IEEE Trans. Image Process. 32: 3679-3689 (2023) - [j110]Yudi Qiu, Jie Jiao, Xiaoyang Zeng, Yibo Fan:
Tag-Sharer-Fusion Directory: A Scalable Coherence Directory With Flexible Entry Formats. IEEE Trans. Parallel Distributed Syst. 34(1): 262-274 (2023) - [j109]Zhijian Hao, Heming Sun, Guoqing Xiang, Peng Zhang, Xiaoyang Zeng, Yibo Fan:
A Reconfigurable Multiple Transform Selection Architecture for VVC. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 658-669 (2023) - [c220]Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu, Xiaoyang Zeng:
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. AICAS 2023: 1-5 - [c219]Yudi Qiu, Shiyan Yi, Ming-e Jing, Xiankui Xiong, Dong Xu, Xuanpeng Zhu, Xiaoyang Zeng, Yibo Fan:
Performance Error Evaluation of gem5 Simulator for ARM Server. ASICON 2023: 1-4 - [c218]Haoyu Wu, Liyu Lin, Haodong Sun, Xiaoyang Zeng, Yun Chen:
A Decision-Based CORDIC Hardware for Arc Tangent Calculation. ASICON 2023: 1-4 - [c217]Zizhao Ma, Xianwu Hu, Gan Wen, Yihao Wang, Zeming Wang, Yukai Lin, Yu Wang, Yuhao Guo, Yanlei Li, Xingdong Liang, Xiaoyang Zeng, Yufeng Xie:
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications. A-SSCC 2023: 1-3 - [c216]Syed Attique Shah, Xiaoyang Zeng, Awais Ahmed, Shaheed Parvez, Rui Xi, Mengshu Hou:
Multi-Instance Bias Suppression for Enhanced Generalization in Breast Cancer Diagnosis : Harnessing Histopathological Big Data Insights. IEEE Big Data 2023: 857-864 - [c215]Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han:
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC 2023: 1-2 - [c214]Yijie Li, Lairong Fang, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 2MHz-BW 96.8dB-SNDR 98dB-SNR CT-Zoom ADC With Residue Feedforward, Redundancy and Fully LMS-Based Calibration. ESSCIRC 2023: 397-400 - [c213]Weili Jin, Xiaoyang Zeng, Ming-e Jing, Jingjing Liu, Mingyu Wang, Wenhong Li:
An Efficient Bundle Adjustment Approach for Stereo Visual Odometry with Pose Consensus. ICCE 2023: 1-6 - [c212]Daobing Zhu, Shu Huan Fan, Xiaoyang Zeng, Rui Xi, Mengshu Hou:
Graph-Attention-Network-Based Cost Estimation Model in Materialized View Environment. ICPADS 2023: 1388-1396 - [c211]Yaoyi Chen, Yujie Huang, Feiqiang Li, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
Denoising Method for Dynamic Vision Sensor Based on Two-Dimensional Event Density. ISCAS 2023: 1-4 - [c210]Aorui Gou, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Fast VVC Intra Encoding for Video Coding for Machines. ISCAS 2023: 1-5 - [c209]Feiqiang Li, Yujie Huang, Yaoyi Chen, Xiaoyang Zeng, Wenhong Li, Mingyu Wang:
Queue-based Spatiotemporal Filter and Clustering for Dynamic Vision Sensor. ISCAS 2023: 1-4 - [c208]Zizhao Ma, Xianwu Hu, Yihao Wang, Gan Wen, Xiaoyang Zeng, Yufeng Xie:
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation. ISCAS 2023: 1-5 - 2022
- [j108]Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu:
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 846-857 (2022) - [j107]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
An Efficient Low-Complexity Convolutional Neural Network Filter. IEEE Multim. 29(2): 83-93 (2022) - [j106]Weina Zhou, Ying Zhou, Xiaoyang Zeng:
An Attention Nested U-Structure Suitable for Salient Ship Detection in Complex Maritime Environment. IEICE Trans. Inf. Syst. 105-D(6): 1164-1171 (2022) - [j105]Weina Zhou, Xinxin Huang, Xiaoyang Zeng:
Obstacle Detection for Unmanned Surface Vehicles by Fusion Refinement Network. IEICE Trans. Inf. Syst. 105-D(8): 1393-1400 (2022) - [j104]Keji Zhou, Ruijun Lin, Zhiwang Guo, Yixuan Liu, Jingwen Jiang, Chenyang Zhao, Jinbei Fang, Xiaoxin Xu, Xiaoyong Xue, Xiaoyang Zeng:
A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. Microelectron. J. 125: 105478 (2022) - [j103]Qi Zheng, Zhengzhong Tu, Xiaoyang Zeng, Alan C. Bovik, Yibo Fan:
Completely Blind Video Quality Evaluator. IEEE Signal Process. Lett. 29: 2228-2232 (2022) - [j102]Ziyu Guo, Weizhen Wang, Xiaodong Wang, Xiaoyang Zeng:
Hardware-Efficient Beamspace Direction-of-Arrival Estimator for Unequal-Sized Subarrays. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1044-1048 (2022) - [j101]Jing Wang, Zhiyuan Chen, Zhen Li, Junmin Jiang, Junrui Liang, Xiaoyang Zeng:
Piezoelectric Energy Harvesters: An Overview on Design Strategies and Topologies. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3057-3063 (2022) - [j100]Yujie Cai, Yibo Fan, Leilei Huang, Xiaoyang Zeng, Haibing Yin, Bing Zeng:
A Fast CABAC Hardware Design for Accelerating the Rate Estimation in HEVC. IEEE Trans. Circuits Syst. Video Technol. 32(4): 2385-2395 (2022) - [j99]Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan:
A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization. IEEE Trans. Circuits Syst. Video Technol. 32(7): 4680-4695 (2022) - [j98]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
QA-Filter: A QP-Adaptive Convolutional Neural Network Filter for Video Coding. IEEE Trans. Image Process. 31: 3032-3045 (2022) - [j97]Yujie Huang, Yuhao Liu, Ming-e Jing, Xiaoyang Zeng, Yibo Fan:
Tear the Image Into Strips for Style Transfer. IEEE Trans. Multim. 24: 3978-3988 (2022) - [c207]Liyu Lin, Junhui Wang, Xiaoyang Zeng, Yun Chen:
An Approximate-Computing-Based Adaptive Equalizer for Polarization Mode Dispersion. APCCAS 2022: 346-349 - [c206]Shaohang Chu, Yan Li, Xu Cheng, Xiaoyang Zeng:
An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. APCCAS 2022: 481-484 - [c205]Tianxiang Qu, Qinjing Pan, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 1.8GΩ-Input-Impedance 0.15µV-Input-Referred-Ripple Chopper Amplifier with Local Positive Feedback and SAR-Assisted Ripple Reduction. CICC 2022: 1-2 - [c204]Peng Cao, Danzhu Lu, Jiawei Xu, Xiaoyang Zeng, Zhiliang Hong:
A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages. ESSCIRC 2022: 277-280 - [c203]Lairong Fang, Yijie Li, Yao Zhang, Shuwen Zhang, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 130μW Three-Step DT Incremental Δ ∑ ADC Achieving 107.6dB DR and 99.3dB SNDR with Zoom and Extended-Range Counting. ESSCIRC 2022: 554-557 - [c202]Qi Zheng, Zhengzhong Tu, Yibo Fan, Xiaoyang Zeng, Alan C. Bovik:
No-Reference Quality Assessment of Variable Frame-Rate Videos Using Temporal Bandpass Statistics. ICASSP 2022: 1795-1799 - [c201]Qi Zheng, Zhengzhong Tu, Zhijian Hao, Xiaoyang Zeng, Alan C. Bovik, Yibo Fan:
Blind Video Quality Assessment via Space-Time Slice Statistics. ICIP 2022: 451-455 - [c200]Chao Liu, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Learned Video Compression With Residual Prediction And Feature-Aided Loop Filter. ICIP 2022: 1321-1325 - [c199]Yi Yang, Zhiyuan Chen, Jingjing Liu, Ziyu Guo, Junmin Jiang, Xiaoyang Zeng:
A Multiple Charge Extractions and Multiple Precharge Interface Circuit for Piezoelectric Energy Harvesting. ISCAS 2022: 1-5 - [c198]Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS 2022: 848-851 - [c197]Yujie Cai, Wei Li, Xiaoyang Zeng, Yibo Fan, Peng Zhang, Guoqing Xiang, Haibing Yin:
A 3.1 Gbin/s advanced entropy coding hardware design for AVS3. ISCAS 2022: 2017-2021 - [c196]Xianwu Hu, Yu Wang, Jiayun Feng, Zizhao Ma, Xiaoyang Zeng, Yufeng Xie:
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process. ISCAS 2022: 2438-2442 - [c195]Liyu Lin, Kaihui Wang, Yun Chen, Jianjun Yu, Xiaoyang Zeng:
A Low-latency Carrier Phase Recovery Hardware for Coherent Optical Communication. ISCAS 2022: 2506-2510 - [c194]Fengshi Tian, Jingwen Jiang, Jinhao Liang, Zhiyuan Zhang, Jiahe Shi, Chaoming Fang, Hui Wu, Xiaoyong Xue, Xiaoyang Zeng:
NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-Memory Engine for EMG Based Hand Gesture Recognition. ISCAS 2022: 2695-2699 - [c193]Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS 2022: 2768-2772 - [c192]Min Li, Jue Wang, Xu Cheng, Xiaoyang Zeng:
A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. ISCAS 2022: 2876-2880 - [c191]Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS 2022: 2933-2937 - [c190]Aorui Gou, Heming Sun, Jiro Katto, Tingting Li, Xiaoyang Zeng, Yibo Fan:
Fast Intra Mode Decision for VVC Based on Histogram of Oriented Gradient. ISCAS 2022: 3028-3032 - [c189]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A QP-adaptive Mechanism for CNN-based Filter in Video Coding. ISCAS 2022: 3195-3199 - [c188]Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu:
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - [c187]Liuhong Chen, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Learning from the NN-based Compressed Domain with Deep Feature Reconstruction Loss. VCIP 2022: 1-5 - [i11]Qi Zheng, Zhengzhong Tu, Pavan C. Madhusudana, Xiaoyang Zeng, Alan C. Bovik, Yibo Fan:
FAVER: Blind Quality Prediction of Variable Frame Rate Videos. CoRR abs/2201.01492 (2022) - [i10]Xiao Yan, Zhangxin Gong, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan:
A high accuracy and low complexity quality control method for image compression. CoRR abs/2210.00821 (2022) - 2021
- [j96]Wei Zhu, Xiaoyang Zeng:
Decision Tree-Based Adaptive Reconfigurable Cache Scheme. Algorithms 14(6): 176 (2021) - [j95]Jingjing Liu, Ruijie Ma, Xiaoyang Zeng, Wanquan Liu, Mingyu Wang, Hui Chen:
An efficient non-convex total variation approach for image deblurring and denoising. Appl. Math. Comput. 397: 125977 (2021) - [j94]Yun Chen, Jimin Wang, Shixian Li, Jinfou Xie, Qichen Zhang, Keshab K. Parhi, Xiaoyang Zeng:
A Reconfigurable 74-140Mbps LDPC Decoding System for CCSDS Standard. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1509-1515 (2021) - [j93]Jingjing Liu, Xianchao Xiu, Xin Jiang, Wanquan Liu, Xiaoyang Zeng, Mingyu Wang, Hui Chen:
Manifold constrained joint sparse learning via non-convex regularization. Neurocomputing 458: 112-126 (2021) - [j92]Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng:
Orthogonal obfuscation based key management for multiple IP protection. Integr. 77: 139-150 (2021) - [j91]Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu:
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. IEEE J. Solid State Circuits 56(3): 988-1000 (2021) - [j90]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110: 105007 (2021) - [j89]Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng:
An energy-efficient crypto-extension design for RISC-V. Microelectron. J. 115: 105165 (2021) - [j88]Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng:
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. 116: 105219 (2021) - [j87]Ming Liu, Ping Zhao, Tianshu Wu, Keshab K. Parhi, Xiaoyang Zeng, Yun Chen:
A low-power twiddle factor addressing architecture for split-radix FFT processor. Microelectron. J. 117: 105276 (2021) - [j86]Zhao Zan, Chao Liu, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Learned Image Compression With Separate Hyperprior Decoders. IEEE Open J. Circuits Syst. 2: 627-632 (2021) - [j85]Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao:
MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications. IEEE Trans. Biomed. Circuits Syst. 15(2): 259-269 (2021) - [j84]Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng:
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2962-2975 (2021) - [j83]Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng:
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 3044-3057 (2021) - [j82]Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng:
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2932-2936 (2021) - [j81]Ziyu Guo, Xiaodong Wang, Xiaoyang Zeng:
Unambiguous Direction-of-Arrival Estimation for Improved Scanning Efficiency in Subarray-Based Hybrid Array. IEEE Trans. Veh. Technol. 70(8): 7966-7979 (2021) - [c186]Wenshu Chen, Liyuan Peng, Yujie Huang, Ming-e Jing, Xiaoyang Zeng:
Knowledge Distillation for U-Net Based Image Denoising. ASICON 2021: 1-4 - [c185]Xi Cheng, Haozhe Zhu, Jingjing Liu, Mingyu Wang, Xiaoyang Zeng:
An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor. ASICON 2021: 1-4 - [c184]Zhijian Hao, Fa Xu, Guoqing Xiang, Peng Zhang, Xiaoyang Zeng, Yibo Fan:
A Multiplier-less Transform Architecture with the Diagonal Data Mapping Transpose Memory for The AVS3 Standard. ASICON 2021: 1-4 - [c183]Xianwu Hu, Dongyang Li, Yu Wang, Jiayun Feng, Zizhao Ma, Shaohao Wang, Tai Min, Xiaoyang Zeng, Yufeng Xie:
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. ASICON 2021: 1-4 - [c182]Yujie Huang, Yixuan Liu, Ming-e Jing, Mingyu Wang, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan:
Arbitrary Style Transfer via Learning to Paint in the Feature Domain. ASICON 2021: 1-4 - [c181]Lixing Li, Deyang Chen, Xiaoyong Xue, Xiaoyang Zeng:
Combining Max Pooling and ReLU Activation Function in Stochastic Computing. ASICON 2021: 1-4 - [c180]Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiaoyang Zeng:
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. ASICON 2021: 1-4 - [c179]Yudi Qiu, Jie Jiao, Yuxin Tang, Yanwei Liu, Jianyu Ren, Xiaoyang Zeng, Yibo Fan:
A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture. ASICON 2021: 1-4 - [c178]Hao Zhang, Aorui Gou, Yibo Fan, Xiaoyang Zeng:
A Fine-grained Sparse Neural Network Accelerator for Image Classification. ASICON 2021: 1-4 - [c177]Ruoyu Zhang, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Small Object Detection in Aerial Images. ASICON 2021: 1-4 - [c176]Hui Zhang, Zhaojie Li, Heqing Yang, Xu Cheng, Xiaoyang Zeng:
A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network. ASICON 2021: 1-4 - [c175]Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Zhiwang Guo, Xiaoyong Xue, Xiaoyang Zeng:
Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications. ASICON 2021: 1-4 - [c174]Yi Zhou, Ming-e Jing, Fa Xu, Yibo Fan, Xiaoyang Zeng:
Mutli-level Regression Anchor-free Object Detection. ASICON 2021: 1-4 - [c173]Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC 2021: 1-3 - [c172]Aorui Gou, Chao Liu, Heming Sun, Xiaoyang Zeng, Yibo Fan:
A-A KD: Attention and Activation Knowledge Distillation. BigMM 2021: 57-60 - [c171]Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori:
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. DATE 2021: 88-93 - [c170]Liuhong Chen, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Fast Object Detection in HEVC Intra Compressed Domain. EUSIPCO 2021: 756-760 - [c169]Yujie Huang, Yi Ling, Ming-e Jing, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan:
Fast Style Transfer with High Shape Retention. ISCAS 2021: 1-5 - [i9]Xiao Yan, Zhixiong Di, Bowen Huang, Minjiang Li, Wenqiang Wang, Xiaoyang Zeng, Yibo Fan:
A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization. CoRR abs/2105.01415 (2021) - [i8]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Learned Video Compression with Residual Prediction and Loop Filter. CoRR abs/2108.08551 (2021) - [i7]Zhao Zan, Chao Liu, Heming Sun, Xiaoyang Zeng, Yibo Fan:
Learned Image Compression with Separate Hyperprior Decoders. CoRR abs/2111.00485 (2021) - 2020
- [j80]Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Chuanjin Richard Shi:
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [j79]Yibo Fan, Leilei Huang, Kewei Chen, Xiaoyang Zeng:
A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM. IEICE Trans. Electron. 103-C(5): 263-273 (2020) - [j78]Zhiyuan Chen, Man-Kay Law, Pui-In Mak, Xiaoyang Zeng, Rui Paulo Martins:
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation. IEEE J. Solid State Circuits 55(8): 2106-2117 (2020) - [j77]Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng:
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2672-2684 (2020) - [j76]Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng:
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1619-1623 (2020) - [j75]Qichen Zhang, Yun Chen, Shixian Li, Xiaoyang Zeng, Keshab K. Parhi:
A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis. IEEE Trans. Circuits Syst. 67-I(12): 5429-5442 (2020) - [j74]Yibo Fan, Yixuan Zeng, Heming Sun, Jiro Katto, Xiaoyang Zeng:
A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3289-3295 (2020) - [j73]Xiao Yan, Yibo Fan, Kewei Chen, Xulin Yu, Xiaoyang Zeng:
QNet: An Adaptive Quantization Table Generator Based on Convolutional Neural Network. IEEE Trans. Image Process. 29: 9654-9664 (2020) - [j72]Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng:
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1089-1093 (2020) - [j71]Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng:
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1423-1434 (2020) - [c168]Xin Shi, Xiaoyang Zeng, Jie Wu, Mengshu Hou, Hao Zhu:
Context Event Features and Event Embedding Enhanced Event Detection. ACAI 2020: 70:1-70:6 - [c167]Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng:
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC 2020: 1-6 - [c166]Minjiang Li, Mingxu Cui, Jun Chi, Xiaoyang Zeng, Ming-e Jing, Yibo Fan:
A Hardware Friendly Haze Removal Method and Its Implementation. ICCE 2020: 1-5 - [c165]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A Learning-Based Low Complexity in-Loop Filter for Video Coding. ICME Workshops 2020: 1-6 - [c164]Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng:
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS 2020: 1-5 - [c163]Jun Chi, Mingjiang Li, Zihao Meng, Yibo Fan, Xiaoyang Zeng, Ming-e Jing:
Single Image Dehazing using a Novel Histogram Tranformation Network. ISCAS 2020: 1-5 - [c162]Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng:
Directly Obtaining Matching Points without Keypoints for Image Stitching. ISCAS 2020: 1-5 - [c161]Zhen Li, Zhiyuan Chen, Qiping Wan, Qin Kuai, Junrui Liang, Philip K. T. Mok, Xiaoyang Zeng:
An Energy Harvesting System with Reconfigurable Piezoelectric Energy Harvester Array for IoT Applications. ISCAS 2020: 1-5 - [c160]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS 2020: 1-5 - [c159]Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu:
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. VLSI Circuits 2020: 1-2 - [i6]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A Convolutional Neural Network-Based Low Complexity Filter. CoRR abs/2009.02733 (2020) - [i5]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A QP-adaptive Mechanism for CNN-based Filter in Video Coding. CoRR abs/2010.13059 (2020)
2010 – 2019
- 2019
- [j70]Jingjing Liu, Donghui He, Xiaoyang Zeng, Mingyu Wang, Xianchao Xiu, Wanquan Liu, Wenhong Li:
ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition. IEEE Access 7: 112939-112952 (2019) - [j69]Yibo Fan, Genwei Tang, Xiaoyang Zeng:
A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder. IEEE Access 7: 149097-149104 (2019) - [j68]Yibo Fan, Yize Jin, Zihao Meng, Xiaoyang Zeng:
Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video\/Image-Based Virtual-Reality Scenes. IEEE Consumer Electron. Mag. 8(2): 44-49 (2019) - [j67]Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng:
A 24-bit sigma-delta ADC with configurable chopping scheme. IEICE Electron. Express 16(10): 20190176 (2019) - [j66]Leilei Huang, Yibo Fan, Chenhao Gu, Xiaoyang Zeng:
A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation. IEICE Trans. Electron. 102-C(10): 756-765 (2019) - [j65]Tianchan Guan, Peiye Liu, Xiaoyang Zeng, Martha A. Kim, Mingoo Seok:
Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2593-2605 (2019) - [j64]Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng:
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2052-2056 (2019) - [j63]Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong:
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 47-56 (2019) - [j62]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 757-768 (2019) - [j61]Liang Wen, Yuejun Zhang, Xiaoyang Zeng:
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1470-1474 (2019) - [c158]Jiawei Wang, Yuejun Zhang, Pengjun Wang, Zhicun Luan, Xiaoyong Xue, Xiaoyang Zeng, Qiaoyan Yu:
An Orthogonal Algorithm for Key Management in Hardware Obfuscation. AsianHOST 2019: 1-4 - [c157]Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng:
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. ASICON 2019: 1-4 - [c156]Jinfou Xie, Shixian Li, Yun Chen, Qichen Zhang, Xiaoyang Zeng:
High throughput multi-code LDPC encoder for CCSDS standard. ASICON 2019: 1-4 - [c155]Yi Zhang, Xiaoshan He, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Enhanced Recursive Residual Network for Single Image Super-Resolution. ASICON 2019: 1-4 - [c154]Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng:
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. ASICON 2019: 1-3 - [c153]Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu:
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. A-SSCC 2019: 29-32 - [c152]Qichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic:
A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. A-SSCC 2019: 271-274 - [c151]Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng:
A Skeleton-based Action Recognition System for Medical Condition Detection. BioCAS 2019: 1-4 - [c150]Huan Tang, Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Very Deep Residual Network for Image Matting. ICIP 2019: 4255-4259 - [c149]Jingjing Liu, Donghui He, Xiaoyang Zeng, Mingyu Wang, Xianchao Xiu, Wanquan Liu, Hui Chen, Yuyao Xiao:
Bayesian Face Recognition Approach Based on Feature Fusion. ICNC-FSKD 2019: 37-45 - [c148]Ping Zhao, Junyi Wang, Xihan Gu, Kangzhou Suo, Yun Chen, Xiaoyang Zeng:
Acoustic Frequency Division Based on Active Metamaterial: An Experimental Demonstration of Acoustic Frequency Halving. IoTaaS 2019: 61-70 - [c147]Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan:
A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture. ISCAS 2019: 1-5 - [c146]Zhiyuan Chen, Yang Jiang, Man-Kay Law, Pui-In Mak, Xiaoyang Zeng, Rui Paulo Martins:
A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement. ISSCC 2019: 424-426 - [c145]Chao Liu, Heming Sun, Junan Chen, Zhengxue Cheng, Masaru Takeuchi, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Dual Learning-based Video Coding with Inception Dense Blocks. PCS 2019: 1-5 - [c144]Yibo Fan, Jiro Katto, Heming Sun, Xiaoyang Zeng, Yixuan Zeng:
A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard. SoCC 2019: 176-180 - [c143]Junan Chen, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient. VCIP 2019: 1-4 - [c142]Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan:
Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding. VCIP 2019: 1-4 - [c141]Chenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC. VLSI-SoC 2019: 269-274 - [i4]Chao Liu, Heming Sun, Junan Chen, Zhengxue Cheng, Masaru Takeuchi, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Dual Learning-based Video Coding with Inception Dense Blocks. CoRR abs/1911.09857 (2019) - 2018
- [j60]Longmei Nan, Xiaoyang Zeng, Wei Li, Zhouchuang Wang, Zibin Dai:
A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications. IEICE Electron. Express 15(5) (2018) - [j59]Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng:
Countering power analysis attacks by exploiting characteristics of multicore processors. IEICE Electron. Express 15(7): 20180084 (2018) - [j58]Chubin Wu, Guangjun Xie, Zhang Zhang, Xin Cheng, Tairan Fei, Jianmin Zeng, Xiaoyang Zeng:
A 15 W wireless power receiver with an improved full-wave synchronous rectifier. IEICE Electron. Express 15(20): 20180732 (2018) - [j57]Yibo Fan, Leilei Huang, Bei Hao, Xiaoyang Zeng:
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation. IEEE Trans. Circuits Syst. Video Technol. 28(8): 2048-2057 (2018) - [c140]Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Ming-e Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu:
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. A-SSCC 2018: 135-138 - [c139]Yujie Huang, Quan Zhang, Yujie Cai, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System. ICA3PP (4) 2018: 3-11 - [c138]Zhengzhong Tu, Tongyu Zong, Xueliang Xi, Li Ai, Yize Jin, Xiaoyang Zeng, Yibo Fan:
Content adaptive tiling method based on user access preference for streaming panoramic video. ICCE 2018: 1-4 - [c137]Tongyu Zong, Zhengzhong Tu, Li Ai, Xueliang Xi, Yize Jin, Xiaoyang Zeng, Yibo Fan:
Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model. ICCE 2018: 1-4 - [c136]Shixian Li, Qichen Zhang, Yun Chen, Xiaoyang Zeng:
A High-Throughput QC-LDPC Decoder for Near-Earth Application. DSP 2018: 1-4 - [c135]Bingyi Zhang, Xin Li, Jun Han, Xiaoyang Zeng:
MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. DSP 2018: 1-5 - [c134]Kewei Chen, Leilei Huang, Minjiang Li, Xiaoyang Zeng, Yibo Fan:
A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture. ICIP 2018: 4168-4172 - [c133]Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu:
An Automatic Task Partition Method for Multi-core System. ISCAS 2018: 1-5 - [c132]Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng:
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. ISOCC 2018: 123-124 - [c131]Sheng Guan, Weicheng He, Wenjin Gu, Yuanzhao Hou, Yun Chen, Xiaoyang Zeng:
Multi-mode Study of Deep Learning Applications in Acoustic Signal Processing. SiPS 2018: 292-295 - 2017
- [j56]Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu:
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14(18): 20170768 (2017) - [j55]Yibo Fan, Leilei Huang, Zheng Xie, Xiaoyang Zeng:
A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding. IEICE Trans. Electron. 100-C(6): 643-654 (2017) - [j54]Liang Wen, Haibo Wen, Xiaoyang Zeng:
Sub-threshold level converter with internal supply feedback for multi-voltage applications. IET Circuits Devices Syst. 11(2): 149-156 (2017) - [c130]Ziqiang Li, Liyu Lin, Yun Chen, Xiaoyang Zeng:
Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output. APCC 2017: 1-5 - [c129]Longmei Nan, Xiaoyang Zeng, Zhouchuang Wang, Yiran Du, Wei Li:
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. ASICON 2017: 191-194 - [c128]Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng:
FPGA-based efficient implementation of SURF algorithm. ASICON 2017: 315-318 - [c127]Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng:
A configurable nonlinear operation unit for neural network accelerator. ASICON 2017: 319-322 - [c126]Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng:
Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm. ASICON 2017: 561-564 - [c125]Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng:
A high utilization FPGA-based accelerator for variable-scale convolutional neural network. ASICON 2017: 944-947 - [c124]Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON 2017: 953-956 - [c123]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Extending memory capacity of neural associative memory based on recursive synaptic bit reuse. DATE 2017: 1603-1606 - [c122]Yize Jin, Liming Wang, Qinwei Jiang, Xiaoyang Zeng, Yibo Fan:
An efficient spherical video sampling scheme based on Cube model. ICCE 2017: 211-214 - [c121]Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng:
Instruction set extension and hardware acceleration for SVM application toward a vector processor. ISOCC 2017: 42-43 - [i3]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement. CoRR abs/1709.05306 (2017) - 2016
- [j53]Xu Cheng, Xiaoyang Zeng, Qi Feng:
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. Microelectron. J. 58: 23-31 (2016) - [j52]Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng:
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 346-350 (2016) - [j51]Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng:
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 643-647 (2016) - [j50]Di Wu, Yun Chen, Qichen Zhang, Yeong-Luh Ueng, Xiaoyang Zeng:
Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 873-877 (2016) - [j49]Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng:
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 984-988 (2016) - [j48]Weiwei Shen, Yibo Fan, Yufeng Bai, Leilei Huang, Qing Shang, Cong Liu, Xiaoyang Zeng:
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC. IEEE Trans. Multim. 18(6): 1022-1033 (2016) - [c120]Shan Huang, Jun Han, Xin Li, Zongxian Yang, Xiaoyang Zeng:
A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. BioCAS 2016: 344-347 - [c119]Qichen Zhang, Yun Chen, Di Wu, Xiaoyang Zeng, Yeong-Luh Ueng:
Convergence-optimized variable node structure for stochastic LDPC decoder. ICASSP 2016: 6535-6539 - [c118]Qinwei Jiang, Leilei Huang, Yibo Fan, Xiaoyang Zeng:
Quarter LCU based integer motion estimation algorithm for HEVC. ICIP 2016: 2018-2021 - [c117]Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng:
Cryptographie coprocessor design for IoT sensor nodes. ISOCC 2016: 37-38 - [c116]Tianchan Guan, Xiaoyang Zeng, Letian Huang, Tianchan Guan, Mingoo Seok:
Neural network based seizure detection system using raw EEG data. ISOCC 2016: 211-212 - 2015
- [j47]Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng:
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12(4): 20150001 (2015) - [j46]Weina Zhou, Huafeng Wu, Xiaoyang Zeng:
A low cost architecture for high performance face detection. Microprocess. Microsystems 39(6): 339-347 (2015) - [j45]Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng:
A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. IEEE Signal Process. Lett. 22(8): 1118-1122 (2015) - [j44]Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng:
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs 62-II(2): 119-123 (2015) - [j43]Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng:
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1372-1381 (2015) - [j42]Yibo Fan, Leilei Huang, Yufeng Bai, Xiaoyang Zeng:
A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1139-1143 (2015) - [j41]Yibo Fan, Qing Shang, Xiaoyang Zeng:
In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding. IEEE Trans. Circuits Syst. Video Technol. 25(1): 112-124 (2015) - [j40]Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 692-701 (2015) - [j39]Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu:
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - [c115]Tianchan Guan, Jun Han, Xiaoyang Zeng:
Exploration for energy-efficient ECC decoder of WBAN. ASICON 2015: 1-4 - [c114]Leilei Huang, Wei Cheng, Xiaoyang Zeng, Yibo Fan:
A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders. ASICON 2015: 1-4 - [c113]Ziqiang Li, Yun Chen, Xiaoyang Zeng:
OFDM synchronization implementation based on Chisel platform for 5G research. ASICON 2015: 1-4 - [c112]YanHeng Lu, Wei Cheng, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A flexible HEVC intra mode decision hardware for 8kx4k real time encoder. ASICON 2015: 1-4 - [c111]Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng:
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON 2015: 1-4 - [c110]Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
Motion artifact removal based on ICA for ambulatory ECG monitoring. ASICON 2015: 1-4 - [c109]Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng:
A SIMD multiplier-accumulator design for pairing cryptography. ASICON 2015: 1-4 - [c108]Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON 2015: 1-4 - [c107]Liang Wen, Li Li, Haibo Wen, Xiaoyang Zeng:
Energy-efficient sub-threshold level shifter. ASICON 2015: 1-4 - [c106]Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
A low-cost SoC implementation of AES algorithm for bio-signals. ASICON 2015: 1-4 - [c105]Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng:
A configurable SoC design for information security. ASICON 2015: 1-4 - [c104]Zhi Hu, Yibo Fan, Xiaoyang Zeng:
Iterative disparity voting based stereo matching algorithm and its hardware implementation. ASP-DAC 2015: 196-201 - [c103]Qichen Zhang, Yun Chen, Di Wu, Xiaoyang Zeng, Yeong-Luh Ueng:
An area-efficient architecture for stochastic LDPC decoder. DSP 2015: 244-247 - [c102]Wei Cheng, Yibo Fan, YanHeng Lu, Yize Jin, Xiaoyang Zeng:
A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application. ISCAS 2015: 605-608 - [c101]Di Wu, Yun Chen, Qichen Zhang, Li-Rong Zheng, Xiaoyang Zeng, Yeong-Luh Ueng:
Latency-optimized stochastic LDPC decoder for high-throughput applications. ISCAS 2015: 3044-3047 - [c100]Yun Chen, Qichen Zhang, Yuanzhou Hu, Na Ding, Xiaoyang Zeng:
An implementation of turbo equalization using cyclic prefix in LTE downlink system. SiPS 2015: 1-4 - [c99]Yun Chen, Yuanzhou Hu, Yizhi Wang, Xiaoyang Zeng, David Huang:
EM independent Gaussian approximate message passing and its application in OFDM impulsive noise mitigation. SoCC 2015: 427-431 - [c98]Wei Li, Xiaoyang Zeng, Xiao Feng, Zibin Dai:
A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance. UIC/ATC/ScalCom 2015: 570-577 - 2014
- [j38]Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014) - [j37]Liang Wen, Zhikui Duan, Yi Li, Xiaoyang Zeng:
Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability. Microelectron. J. 45(6): 815-824 (2014) - [j36]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014) - [j35]Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng:
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(6): 423-427 (2014) - [j34]Yun Chen, Qichen Zhang, Di Wu, Changsheng Zhou, Xiaoyang Zeng:
An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 992-996 (2014) - [j33]Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng:
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2245-2255 (2014) - [j32]Qing Shang, Yibo Fan, Weiwei Shen, Sha Shen, Xiaoyang Zeng:
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2422-2426 (2014) - [c97]Mengyuan Chen, Jun Han, Yicheng Zhang, Yao Zou, Yi Li, Xiaoyang Zeng:
An error-resilient wavelet-based ECG processor under voltage overscaling. BioCAS 2014: 628-631 - [c96]Lijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng:
Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. ISIC 2014: 344-347 - [c95]Weiwei Shen, Yibo Fan, Leilei Huang, Jiali Li, Xiaoyang Zeng:
A hardware-friendly method for rate-distortion optimization of HEVC intra coding. VLSI-DAT 2014: 1-4 - 2013
- [j31]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC. IEICE Electron. Express 10(11): 20130272 (2013) - [j30]Yun Chen, Xubin Chen, Zhiyuan Guo, Xiaoyang Zeng, Defeng Huang:
A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced. IEICE Trans. Commun. 96-B(5): 1211-1214 (2013) - [j29]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A Unified Forward/Inverse Transform Architecture for Multi-Standard Video Codec Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1534-1542 (2013) - [j28]Yue Wu, Xu Cheng, Xiaoyang Zeng:
A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. Microelectron. J. 44(12): 1260-1267 (2013) - [j27]Yao Zou, Jun Han, Xinqian Weng, Xiaoyang Zeng:
An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform. IEEE Signal Process. Lett. 20(5): 515-518 (2013) - [j26]Chen Chen, Yun Chen, Na Ding, Yizhi Wang, Jia-Chin Lin, Xiaoyang Zeng, Defeng David Huang:
Accurate Sampling Timing Acquisition for Baseband OFDM Power-Line Communication in Non-Gaussian Noise. IEEE Trans. Commun. 61(4): 1608-1620 (2013) - [j25]Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng:
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2325-2330 (2013) - [c94]Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng:
A hardware-efficient variable-length FFT processor for low-power applications. APSIPA 2013: 1-4 - [c93]Mengyuan Chen, Jun Han, Dabin Fang, Yao Zou, Xiaoyang Zeng:
An ultra low-power and area-efficient baseband processor for WBAN transmitter. APSIPA 2013: 1-4 - [c92]Jie Cheng, Yun Chen, Wenxu Bao, Yuanzhou Hu, Na Ding, Xiaoyang Zeng:
Positionable wearable fall detection system for elderly assisted living applications. ASICON 2013: 1-4 - [c91]Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng:
Design of a high throughput configurable variable-length FFT processor based on switch network architecture. ASICON 2013: 1-4 - [c90]Tianchan Guan, Jun Han, Xiaoyang Zeng:
Highly flexible WBAN transmit-receive system based on USRP. ASICON 2013: 1-4 - [c89]Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng:
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. ASICON 2013: 1-4 - [c88]Cong Liu, Weiwei Shen, Tianlong Ma, Yibo Fan, Xiaoyang Zeng:
A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. ASICON 2013: 1-4 - [c87]Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng:
A fast 8×8 IDCT algorithm for HEVC. ASICON 2013: 1-4 - [c86]Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng:
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON 2013: 1-4 - [c85]Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng:
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. ASICON 2013: 1-4 - [c84]Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A fast multi-core virtual platform and its application on software development. ASICON 2013: 1-4 - [c83]Di Wu, Yun Chen, Yuebin Huang, Yeong-Luh Ueng, Li-Rong Zheng, Xiaoyang Zeng:
A high-throughput LDPC decoder for optical communication. ASICON 2013: 1-4 - [c82]Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng:
Low power design for FIR filter. ASICON 2013: 1-4 - [c81]Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
Efficient implementation of 3780-point FFT on a 16-core processor. ASICON 2013: 1-4 - [c80]Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. ASICON 2013: 1-4 - [c79]Dexue Zhang, Xiaoyang Zeng, Zongyan Wang, Weike Wang, Xinhua Chen:
MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support. ASICON 2013: 1-4 - [c78]Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng:
A 2D mesh NoC with self-configurable and shared-FIFOs routers. ASICON 2013: 1-4 - [c77]Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng:
H.264 video parallel decoder on a 24-core processor. ASICON 2013: 1-4 - [c76]Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng:
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS 2013: 154-157 - [c75]Shuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng:
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. CICC 2013: 1-4 - [c74]Yun Chen, Changsheng Zhou, Yuebin Huang, Xiaoyang Zeng:
An efficient multi-rate LDPC-CC decoder with layered decoding algorithm. ICC 2013: 5548-5552 - [c73]Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu:
A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. ISCAS 2013: 349-352 - [c72]Weiwei Shen, Qing Shang, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A high-throughput VLSI architecture for deblocking filter in HEVC. ISCAS 2013: 673-676 - [c71]Jianfei Xu, Na Yan, Qiang Chen, Jianjun Gao, Xiaoyang Zeng:
A 3.4dB NF k-band LNA in 65nm CMOS technology. ISCAS 2013: 1123-1126 - [c70]Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Liyang Zhou:
Time-Division-Multiplexer based routing algorithm for NoC system. ISCAS 2013: 1652-1655 - [c69]Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Jiayi Sheng, Haofan Yang:
Implementation and optimization of 3780-point FFT on multi-core system. ISCAS 2013: 1656-1659 - [c68]Yue Wu, Xu Cheng, Xiaoyang Zeng:
A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. ISCAS 2013: 2014-2017 - [c67]Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. ISSCC 2013: 56-57 - [c66]Yun Chen, Qiang Zhang, Yunlong Ge, Yuanzhou Hu, Jie Chen, Na Ding, Xiaoyang Zeng, Defeng Huang:
Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC. MWSCAS 2013: 932-935 - [c65]Chen Chen, Yun Chen, Na Ding, Qiang Zhang, Wenxu Bao, Yuanzhou Hu, Xiaoyang Zeng:
Fine residual carrier frequency and sampling frequency estimation in wireless OFDM systems. MWSCAS 2013: 1124-1127 - [c64]Dabin Fang, Huikai Li, Jun Han, Xiaoyang Zeng:
Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks. NAS 2013: 178-186 - 2012
- [j24]Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9(16): 1355-1361 (2012) - [j23]Weina Zhou, Lin Dai, Yao Zou, Xiaoyang Zeng, Jun Han:
A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. IEICE Trans. Inf. Syst. 95-D(2): 383-391 (2012) - [j22]Shuangqu Huang, Xiaoyang Zeng, Yun Chen:
A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms. IEICE Trans. Inf. Syst. 95-D(2): 403-412 (2012) - [j21]Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K × 2 K Applications. IEICE Trans. Electron. 95-C(4): 441-446 (2012) - [j20]Yibo Fan, Jialiang Liu, Dexue Zhang, Xiaoyang Zeng, Xinhua Chen:
An 8 × 4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4 K × 2 K H.264/AVC Encoder. IEICE Trans. Electron. 95-C(4): 447-455 (2012) - [j19]Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Yun Chen, Xiaoyang Zeng:
An Area-Efficient Reconfigurable LDPC Decoder with Conflict Resolution. IEICE Trans. Electron. 95-C(4): 478-486 (2012) - [j18]Wenhua Fan, Chen Chen, Yun Chen, Zhiyi Yu, Xiaoyang Zeng:
Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. IEICE Trans. Commun. 95-B(4): 1241-1248 (2012) - [j17]Yuli Zhang, Jun Han, Xinqian Weng, Zhongzhu He, Xiaoyang Zeng:
Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm. IEICE Trans. Electron. 95-C(8): 1415-1426 (2012) - [j16]Yun Chen, Yuebin Huang, Chen Chen, Changsheng Zhou, Xiaoyang Zeng:
A Flexible Architecture for TURBO and LDPC Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2392-2395 (2012) - [j15]Bei Huang, Kaidi You, Yun Chen, Zhiyi Yu, Xiaoyang Zeng:
A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. IEICE Trans. Inf. Syst. 95-D(12): 2939-2947 (2012) - [c63]Yifan Bo, Jun Han, Yao Zou, Xiaoyang Zeng:
A low power ASIP for precision configurable FFT processing. APSIPA 2012: 1-4 - [c62]Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng:
A 60mW baseband SoC for CMMB receiver. ASP-DAC 2012: 479-480 - [c61]Dan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiaoyang Zeng:
A single-routing layered LDPC decoder for 10Gbase-T Ethernet in 130nm CMOS. ASP-DAC 2012: 565-566 - [c60]Huailu Ren, Yibo Fan, Xinhua Chen, Xiaoyang Zeng:
A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder. ASP-DAC 2012: 801-806 - [c59]Sha Shen, Weiwei Shen, Yibo Fan, Xiaoyang Zeng:
A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards. ICME 2012: 788-793 - [c58]Liyang Zhou, Ming-e Jing, Liulin Zhong, Zhiyi Yu, Xiaoyang Zeng:
Task-binding based branch-and-bound algorithm for NoC mapping. ISCAS 2012: 648-651 - [c57]Huibo Zhong, Yibo Fan, Xiaoyang Zeng:
A parallel CAVLC design for 4096×2160p encoder. ISCAS 2012: 1432-1435 - [c56]Na Ding, Chen Chen, Wenhua Fan, Yun Chen, Xiaoyang Zeng:
An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems. ISCAS 2012: 1516-1519 - [c55]Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. ISCAS 2012: 2609-2612 - [c54]Yueming Yang, Zewen Shi, Jianming Yu, Liulin Zhong, Xiaoyang Zeng, Zhiyi Yu:
Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability. ISCAS 2012: 2713-2716 - [c53]Enle Chen, Yun Chen, Yizhi Wang, Chen Chen, Xiaoyang Zeng:
A multi-core mapping implementation of 3780-point FFT. ISOCC 2012: 289-292 - [c52]Yun Chen, Yuebin Huang, Wei Meng, Zhiyi Yu, Xiaoyang Zeng:
A low-cost architecture for multi-mode Reed-Solomon decoder. ISOCC 2012: 332-334 - [c51]Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng:
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. ISSCC 2012: 64-66 - [c50]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A Low Complexity Macroblock Layer Rate Control Scheme Base on Weighted-Window for H.264 Encoder. MMM 2012: 563-573 - [i2]Chen Chen, Yun Chen, Yizhi Wang, Na Ding, Jia-Chin Lin, Xiaoyang Zeng, Defeng David Huang:
Accurate Sampling Timing Acquisition for Baseband OFDM Power-line Communication in Non-Gaussian Noise. CoRR abs/1211.1819 (2012) - [i1]Chen Chen, Yun Chen, Xiaoyang Zeng:
Fine Residual Carrier Frequency and Sampling Frequency Estimation in Wireless OFDM Systems. CoRR abs/1211.1830 (2012) - 2011
- [j14]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A 4-way parallel CAVLC design for H.264/AVC 4Kx2K 60fps encoder. IEICE Electron. Express 8(22): 1863-1869 (2011) - [j13]Yibo Fan, Xiaoyang Zeng, Satoshi Goto:
Optimized 2-D SAD Tree Architecture of Integer Motion Estimation for H.264/AVC. IEICE Trans. Electron. 94-C(4): 411-418 (2011) - [j12]Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs. IEICE Trans. Inf. Syst. 94-D(7): 1386-1397 (2011) - [j11]Chuan Wu, Dan Bao, Xiaoyang Zeng, Yun Chen:
Efficient Iterative Frequency Domain Equalization for Single Carrier System with Insufficient Cyclic Prefix. IEICE Trans. Commun. 94-B(7): 2174-2177 (2011) - [j10]Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng:
An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(6): 1416-1432 (2011) - [c49]Changsheng Zhou, Yunlong Ge, Xubin Chen, Yun Chen, Xiaoyang Zeng:
An area-Efficient LDPC decoder for multi-standard with conflict resolution. ASAP 2011: 105-112 - [c48]Sha Shen, Huibo Zhong, Yibo Fan, Xiaoyang Zeng:
A hardware/software co-design approach for multiple-standard video bitstream parsing. ASICON 2011: 43-46 - [c47]Junbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng:
Analysis of adaptive support-weight based stereo matching for hardware realization. ASICON 2011: 51-54 - [c46]Huibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng:
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC. ASICON 2011: 75-78 - [c45]Weina Zhou, Yao Zou, Lin Dai, Xiaoyang Zeng:
A high speed reconfigurable face detection architecture. ASICON 2011: 83-86 - [c44]Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng:
A NoC-based multi-core architecture for IEEE 802.11i CCMP. ASICON 2011: 196-199 - [c43]Jiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A method of quadratic programming for mapping on NoC architecture. ASICON 2011: 200-203 - [c42]Maofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng:
A channel estimator for LTE downlink mapped on a multi-core processor platform. ASICON 2011: 204-207 - [c41]Chen Chen, Yuebin Huang, Yizhi Wang, Yun Chen, Xiaoyang Zeng:
A robust frame synchronization scheme for Broadband Power-line Communication. ASICON 2011: 212-215 - [c40]Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. ASICON 2011: 267-270 - [c39]Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Design of a single-ended cell based 65nm 32×32b 4R2W register file. ASICON 2011: 311-314 - [c38]Liulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou:
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. ASICON 2011: 389-392 - [c37]Hong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng:
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. ASICON 2011: 465-468 - [c36]Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng:
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. ASICON 2011: 484-487 - [c35]Li Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng:
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. ASICON 2011: 504-507 - [c34]Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng:
A control scheme for a 65nm 32×32b 4-read 2-write register file. ASICON 2011: 739-742 - [c33]Shuai Wang, Yang Li, Junbao Liu, Jun Han, Xiaoyang Zeng:
A security processor based on MIPS 4KE architecture. ASICON 2011: 751-754 - [c32]Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A low power 1.0 GHz VCO in 65nm-CMOS LP-process. ASICON 2011: 1006-1009 - [c31]Dan Bao, Chuan Wu, Yan Ying, Yun Chen, Xiaoyang Zeng:
A 4.32 mm2 170mW LDPC decoder in 0.13μm CMOS for WiMax/Wi-Fi applications. ASP-DAC 2011: 77-78 - [c30]Yizhi Wang, Yun Chen, Yunlong Ge, Huxiong Xu, Xiaoyang Zeng:
A channel estimation scheme for Chinese DTTB system combating long echo and high doppler shift. ISCAS 2011: 462-465 - [c29]Zhiyi Yu, Zewen Shi, Xiaoyang Zeng:
Fault tolerant computing for stream DSP applications using GALS multi-core processors. ISCAS 2011: 2305-2308 - [c28]Zewen Shi, Yueming Yang, Xiaoyang Zeng, Zhiyi Yu:
A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. ISCAS 2011: 2934-2937 - [c27]Yun Chen, Changsheng Zhou, Yuebin Huang, Shuangqu Huang, Xiaoyang Zeng:
Flexible and efficient FEC decoders supporting multiple transmission standards. ISOCC 2011: 48-53 - [c26]Yuebin Huang, Chen Chen, Changsheng Zhou, Yun Chen, Xiaoyang Zeng:
A common flexible architecture for Turbo/LDPC codes. ISOCC 2011: 54-57 - [c25]Jiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng:
MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoder. VLSI-SoC 2011: 72-77 - [c24]Jialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng:
A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoder. VLSI-SoC 2011: 434-439 - 2010
- [j9]Yan Ying, Dan Bao, Zhiyi Yu, Xiaoyang Zeng, Yun Chen:
A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(8): 1415-1424 (2010) - [j8]Dan Bao, Bo Xiang, Rui Shen, An Pan, Yun Chen, Xiaoyang Zeng:
Programmable Architecture for Flexi-Mode QC-LDPC Decoder Supporting Wireless LAN/MAN Applications and Beyond. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 125-138 (2010) - [j7]Yunlong Ge, Huxiong Xu, Yun Chen, Yizhi Wang, Xiaoyang Zeng:
Low cost VLSI architecture of resisting long echo channel estimation for DTMB system. IEEE Trans. Consumer Electron. 56(3): 1247-1251 (2010) - [j6]Chuan Wu, Dan Bao, Xiaoyang Zeng, Bo Shen:
An efficient iterative frequency domain equalization for ATSC DTV receiver. IEEE Trans. Consumer Electron. 56(4): 2148-2154 (2010) - [j5]Bo Xiang, Rui Shen, An Pan, Dan Bao, Xiaoyang Zeng:
An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1447-1460 (2010) - [c23]Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng:
A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications. ASAP 2010: 225-232 - [c22]Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu:
A scalable and fault-tolerant routing algorithm for NoCs. ISCAS 2010: 165-168 - [c21]Simeng Li, Huxiong Xu, Wenhua Fan, Yun Chen, Xiaoyang Zeng:
A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e. ISCAS 2010: 1488-1491 - [c20]Shuangqu Huang, Dan Bao, Bo Xiang, Yun Chen, Xiaoyang Zeng:
A flexible LDPC decoder architecture supporting two decoding algorithms. ISCAS 2010: 3929-3932 - [c19]Yulong Zhang, Xubin Chen, Wenhua Fan, Jun Han, Xiaoyang Zeng:
Robust and reliable frame synchronization method for DVB-S2 system. WTS 2010: 1-5 - [c18]Yulong Zhang, Jialin Cao, Chuan Wu, Jun Han, Xiaoyang Zeng:
Optimized digital automatic gain control for DVB-S2 system. WTS 2010: 1-5
2000 – 2009
- 2009
- [c17]Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu:
A multi-task-oriented security processing architecture with powerful extensibility. ASP-DAC 2009: 133-134 - 2008
- [j4]Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications. IEEE J. Solid State Circuits 43(2): 321-329 (2008) - [j3]Hao Xiao, An Pan, Yun Chen, Xiaoyang Zeng:
Low-cost reconfigurable VLSI architecture for fast fourier transform. IEEE Trans. Consumer Electron. 54(4): 1617-1622 (2008) - [c16]Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao:
A low-cost cryptographic processor for security embedded system. ASP-DAC 2008: 113-114 - [c15]Li Qing, Xiaoyang Zeng, Chuan Wu, Yulong Zhang, Yunsong Deng, Jun Han:
Optimal frame synchronization for DVB-S2. ISCAS 2008: 956-959 - [c14]Daxian Yun, Yanjie Peng, Jun Han, Xiaoyang Zeng:
Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. ISCAS 2008: 2490-2493 - [c13]Liang Li, Jun Han, Xiaoyang Zeng, Jia Zhao:
A full-custom design of AES SubByte module with signal independent power consumption. ISCAS 2008: 3302-3305 - [c12]Yanjie Peng, Lang Mai, Xiaoyang Zeng:
Low-complexity two-stage timing acquisition scheme for UWB communications. WTS 2008: 53-56 - 2007
- [j2]Yun Chen, Xiaoyang Zeng, An Pan, Jing Wang:
A Novel Five-Point Algorithm of Phase Noise Cancellation in DTMB. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(11): 2608-2611 (2007) - [j1]Jianming Wu, Yun Chen, Xiaoyang Zeng, Hao Min:
Robust Timing and Frequency Synchronization Scheme for DTMB System. IEEE Trans. Consumer Electron. 53(4): 1348-1352 (2007) - [c11]Jing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng:
An Energy-Proportion Synchronization Method for IR-UWB Communications. ISCAS 2007: 2578-2581 - [c10]Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao:
A Low-cost and High-performance SoC Design for OMA DRM2 Applications. ISCAS 2007: 3510-3513 - [c9]Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng:
Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation. SiPS 2007: 151-156 - 2006
- [c8]Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan:
A high-performance platform-based SoC for information security. ASP-DAC 2006: 122-123 - [c7]Jian Li, Xiaoyang Zeng, Lei Xie, Jun Chen, Jianyun Zhang, Yawei Guo:
A 1.8-V 22-mW 10-bit 30-MS/s Subsampling Pipelined CMOS ADC. CICC 2006: 513-516 - [c6]Yibo Fan, Xiaoyang Zeng, Yu Yu, Gang Wang, Qianling Zhang:
A modified high-radix scalable Montgomery multiplier. ISCAS 2006 - [c5]Yongxin Ma, Xiaoyang Zeng, Min Wu, Chengshou Sun:
A new low cost and reconfigurable RSA crypto-processor. ISCAS 2006 - [c4]Yongyi Wu, Xiaoyang Zeng:
A new dual-field elliptic curve cryptography processor. ISCAS 2006 - [c3]Jiefeng Yan, Lei Xie, Xiaoyang Zeng, Tingao Tang:
Adaptive bandwidth PLL with compact current mode filter. ISCAS 2006 - 2005
- [c2]Jian Li, Jianyun Zhang, Bo Shen, Xiaoyang Zeng, Yawei Guo, Tingao Tang:
A 10BIT 30MSPS CMOS A/D converter for high performance video applications. ESSCIRC 2005: 523-526 - [c1]Yibo Fan, Xiaoyang Zeng, Zhang Zhang, Jun Chen, Qianling Zhang:
VLSI design of a high-speed RAS crypto-processor with reconfigurable architecture. ISSPA 2005: 307-310
Coauthor Index
[c207] [c195] [j94] [j87] [j75] [c156] [c152] [c148] [c136] [c131] [c130] [j50] [c119] [c113] [c103] [c101] [c100] [c99] [j34] [j30] [j26] [c92] [c83] [c74] [c66] [c65] [j22] [j19] [j18] [j16] [j15] [c62] [c61] [c56] [c53] [c52] [i2] [i1] [j11] [c49] [c41] [c31] [c30] [c27] [c26] [j9] [j8] [j7] [c21] [c20] [j3] [j2] [j1]
[j149] [j146] [j136] [j134] [j132] [c231] [c227] [c226] [j123] [j113] [j110] [j109] [c219] [c210] [j107] [j103] [j100] [j99] [j98] [j97] [c202] [c201] [c200] [c197] [c190] [c189] [c187] [i11] [i10] [j86] [c184] [c182] [c179] [c178] [c177] [c174] [c172] [c170] [c169] [i9] [i8] [i7] [j79] [j74] [j73] [c166] [c165] [c163] [c162] [i6] [i5] [j69] [j68] [j66] [c155] [c150] [c147] [c145] [c144] [c143] [c142] [c141] [i4] [j57] [c139] [c138] [c137] [c134] [c133] [c132] [j55] [c122] [j48] [c118] [j42] [j41] [c114] [c112] [c104] [c102] [j32] [c95] [j31] [j29] [c88] [c87] [c72] [j21] [j20] [c60] [c59] [c57] [c50] [j14] [j13] [c48] [c46] [c25] [c24] [c8] [c6] [c1]
[j142] [j140] [j131] [j129] [j128] [c232] [c222] [j121] [j120] [j119] [c215] [c198] [c193] [c191] [j90] [j89] [j88] [j85] [j84] [j83] [j82] [c173] [c171] [j77] [j76] [j72] [j71] [c167] [c164] [c160] [j64] [c154] [c151] [j59] [c135] [c132] [j56] [c128] [c127] [c126] [c125] [c124] [c121] [j49] [c120] [c117] [j45] [j44] [j43] [j40] [j39] [c115] [c111] [c110] [c109] [c108] [c106] [c105] [j38] [j36] [j33] [c97] [j27] [j25] [c94] [c93] [c91] [c90] [c86] [c82] [c76] [c75] [c64] [j24] [j23] [j17] [c63] [c47] [c44] [c39] [c34] [c33] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c11] [c10] [c9] [c8]
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