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ORCIDShiwei Liu 0002
Person information
- affiliation: Fudan University, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
Other persons with the same name
- Shiwei Liu (aka: Shi-Wei Liu) — disambiguation page
- Shiwei Liu 0001
![[0000-0002-5389-1930]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-5389-1930")
— Huazhong Agricultural University, College of Engineering, Wuhan, China - Shiwei Liu 0003 — University of Oxford, Mathematical Institute, UK (and 2 more)
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2020 – today
- 2024
[j2]Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen:
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 269-282 (2024)- 2023
- [c5]Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen:
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS 2023: 1-5 - [c4]Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang, Haozhe Zhu, Wenning Jiang, Shan Tang, Chixiao Chen, Qi Liu, Ming Liu:
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC 2023: 250-251 - 2022
- [c3]Chen Mu, Yunzhengmao Wang, Jiapei Zheng, Shiwei Liu, Keji Zhou, Shan Tang, Chixiao Chen, Qi Liu:
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS 2022: 222-225 - 2021
- [c2]Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, Chuanjin Richard Shi:
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. ACM Great Lakes Symposium on VLSI 2021: 353-358 - 2020
- [j1]Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Chuanjin Richard Shi:
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [c1]Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, Chuanjin Richard Shi:
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS 2020: 21-25
Coauthor Index
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