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ORCIDJinshan Zhang 0006
Person information
- affiliation: Fudan University, Shanghai Engineering Research Center of AI & Robotics, Shanghai, China
Other persons with the same name
- Jinshan Zhang 0001
![[0000-0003-3427-9014]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-3427-9014")
— Zhejiang University, Hangzhou, China (and 2 more) - Jinshan Zhang 0002 — Inner Mongolia University of Science and Technology, School of Mines and Coal, Baotou, China
- Jinshan Zhang 0003 — Nanjing Hydraulic Research Institute, China
- Jinshan Zhang 0004 — Sichuan University of Science and Engineering, School of Science, Zigong, China
- Jinshan Zhang 0005 — Shandong University, School of Mechanical, Electrical and Information Engineering, Weihai, China
- Jinshan Zhang 0007 — Hohai University, College of Hydrology and Water Resources, Nanjing, China
- Jinshan Zhang 0008 — Jilin University, School of Business and Management, Changchun, China
- Jinshan Zhang 0009 — University of Jinan, School of Information Science and Engineering, China
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2020 – today
- 2024
[j1]Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen:
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 269-282 (2024)- 2023
- [c8]Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu:
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS 2023: 1-5 - [c7]Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen:
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS 2023: 1-5 - [c6]Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang, Haozhe Zhu, Wenning Jiang, Shan Tang, Chixiao Chen, Qi Liu, Ming Liu:
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC 2023: 250-251 - 2022
- [c5]Xinru Jia, Haozhe Zhu, Yunzheng Wang, Jinshan Zhang, Feng Lin, Xiankui Xiong, Dong Xu, Chixiao Chen, Qi Liu:
A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. ISCAS 2022: 2816-2820 - [c4]Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu:
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC 2022: 1-3 - 2021
- [c3]Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen:
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. ASP-DAC 2021: 13-14 - [c2]Bo Jiao, Haozhe Zhu, Jinshan Zhang, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang, Chixiao Chen:
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. ACM Great Lakes Symposium on VLSI 2021: 241-246 - [c1]Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang, Chixiao Chen:
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. ACM Great Lakes Symposium on VLSI 2021: 333-338
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