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ORCIDJun Han 0003
Person information
- affiliation: Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
Other persons with the same name
- Jun Han — disambiguation page
- Jun Han 0001
![[0000-0003-0798-704X]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-0798-704X")
— Yonsei University, School of Electrical and Electronic Engineering, Seoul, South Korea (and 2 more) - Jun Han 0002 — Dartmouth College, USA
- Jun Han 0004 — Swinburne University of Technology, Hawthorn, VIC, Australia
- Jun Han 0005 — Capital Normal University, College of Education, Beijing, China
- Jun Han 0006 — Bond University, QLD, Australia
- Jun Han 0007 — University of Georgia, Athens, GA, USA
- Jun Han 0008 — University of California, San Diego, La Jolla, CA, USA
- Jun Han 0009 — Dortmund University of Technology, Germany
- Jun Han 0010 — Chinese University of Hong Kong-Shenzhen (CUHK-SZ), Shenzhen, China (and 1 more)
- Jun Han 0011 — University of Queensland, Australia
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2020 – today
- 2024
[j47]Zhen Li, Jing Wang, Man-Kay Law, Sijun Du, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng, Zhiyuan Chen:
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. IEEE J. Solid State Circuits 59(7): 2248-2259 (2024)- [j46]Chenyang Zhao, Jinbei Fang, Xiaoli Huang, Deyang Chen, Zhiwang Guo, Jingwen Jiang, Jiawei Wang, Jianguo Yang, Jun Han, Peng Zhou, Xiaoyong Xue, Xiaoyang Zeng:
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications. IEEE J. Solid State Circuits 59(10): 3277-3289 (2024) - [j45]Yitong Rong, Xuyang Duan, Jun Han:
A high-throughput and low-storage stereo vision accelerator with dependency-resolving strided aggregation for 8-path semi-global matching. Microelectron. J. 146: 106156 (2024) - [j44]Yongliang Zhang, Yitong Rong, Xuyang Duan, Zhen Yang, Qiang Li, Ziyu Guo, Xu Cheng, Xiaoyang Zeng, Jun Han:
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 320-333 (2024) - [j43]Yuanyuan Han, Xu Cheng, Xiaoyong Xue, Jun Han, Jiawei Xu, Xiaoyang Zeng:
SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1416-1420 (2024) - [j42]Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng:
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024) - [j41]Ziyu Guo, Tao Yang, Peng Chen, Jun Han, Xiaoyang Zeng, Bo Hu:
Angular Parameter Estimation for Incoherently Distributed Sources With Single RF Chain. IEEE Trans. Signal Process. 72: 5244-5257 (2024) - [j40]Zikang Zhou, Xuyang Duan, Jun Han:
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1485-1497 (2024) - [c73]Lizhou Wu, Chenyang Zhao, Jingbo Wang, Xueru Yu, Shoumian Chen, Chen Li, Jun Han, Xiaoyong Xue, Xiaoyang Zeng:
A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications. ASPDAC 2024: 551-556 - [c72]Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang, Jun Han:
RVCE-FAL: A RISC-V Scalar-Vector Custom Extension for Faster FALCON Digital Signature. DATE 2024: 1-6 - [c71]Chao Fu, Zengshi Wang, Jun Han:
Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification. FPL 2024: 133-139 - [c70]Zikang Zhou, Xuyang Duan, Kaiqi Chen, Yaqi Chen, Jun Han:
ML-Fusion: Determining Memory Levels for Data Reuse Between DNN Layers. ACM Great Lakes Symposium on VLSI 2024: 63-68 - [c69]Li Wan, Fu Chao, Qiang Li, Jun Han:
LockillerTM: Enhancing Performance Lower Bounds in Best-Effort Hardware Transactional Memory. IPDPS 2024: 865-875 - [c68]Xinhao Mao, Ziyu Guo, Jun Han, Bo Hu, Xiaoyang Zeng:
Hardware Acceleration of Phase and Gain Control for Analog Beamforming. ISCAS 2024: 1-5 - 2023
- [j39]Qiang Li, Jun Tao, Jun Han:
SPARK: An automatic Score-Power-Area efficient RISC-V processor microarchitecture SeeKer. Microelectron. J. 132: 105679 (2023) - [j38]Song Wang, Xu Cheng, Ziyu Guo, Jun Han:
A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. Microelectron. J. 136: 105778 (2023) - [j37]Xuyang Duan, Yufan Chen, Menghan Li, Yitong Rong, Ruiqi Xie, Jun Han:
UArch: A Super-Resolution Processor With Heterogeneous Triple-Core Architecture for Workloads of U-Net Networks. IEEE Trans. Biomed. Circuits Syst. 17(3): 633-647 (2023) - [j36]Yan Liu, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1639-1648 (2023) - [j35]Yan Li, Chao Chen, Xu Cheng, Jun Han, Xiaoyang Zeng:
DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 4015-4027 (2023) - [j34]Baijie Zhang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5242-5253 (2023) - [c67]Yifan Zhao, Honglin Kuang, Yi Sun, Zhen Yang, Chen Chen, Jianyi Meng, Jun Han:
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography. ASAP 2023: 10-17 - [c66]Yufan Chen, Xuyang Duan, Jun Han:
UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN. ASICON 2023: 1-4 - [c65]Honglin Kuang, Yifan Zhao, Yi Sun, Jun Han:
General Vector Instruction Extension for GF(2m) Polynomial Operation in Post-quantum Cryptography. ASICON 2023: 1-4 - [c64]Zengshi Wang, Chao Fu, Jun Han:
Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System. ASICON 2023: 1-4 - [c63]Zhen Li, Zhiyuan Chen, Man-Kay Law, Sijun Du, Xu Cheng, Xiaoyang Zeng, Jun Han:
A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. CICC 2023: 1-2 - [c62]Kaixuan Wang, Xinyu Qin, Zhuoyuan Yang, Weiliang He, Yifan Liu, Jun Han:
SVP: Safe and Efficient Speculative Execution Mechanism through Value Prediction. ACM Great Lakes Symposium on VLSI 2023: 433-437 - 2022
- [j33]Yifan Zhao, Ruiqi Xie, Guozhu Xin, Jun Han:
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2871-2884 (2022) - [j32]Chao Fu, Li Wan, Jun Han:
LosaTM: A Hardware Transactional Memory Integrated With a Low-Overhead Scenario-Awareness Conflict Manager. IEEE Trans. Parallel Distributed Syst. 33(12): 4849-4862 (2022) - [c61]Honglin Kuang, Yifan Zhao, Jun Han:
A High-Speed NTT-Based Polynomial Multiplication Accelerator with Vector Extension of RISC-V for Saber Algorithm. APCCAS 2022: 592-595 - [c60]Baijie Zhang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. ISCAS 2022: 848-851 - [c59]Jing Wang, Zhiyuan Chen, Junrui Liang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. ISCAS 2022: 2768-2772 - [c58]Jiawei Wang, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. ISCAS 2022: 2933-2937 - 2021
- [j31]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110: 105007 (2021) - [j30]Weizhen Wang, Jun Han, Xu Cheng, Xiaoyang Zeng:
An energy-efficient crypto-extension design for RISC-V. Microelectron. J. 115: 105165 (2021) - [j29]Yong-Liang Zhang, Qiang Li, Hui Zhang, Wei-Zhen Wang, Jun Han, Xiaoyang Zeng, Xu Cheng:
A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. Microelectron. J. 116: 105219 (2021) - [j28]Chao Fu, Yuchao Zhou, Jun Han:
A hardware-efficient dual-source data replication and local broadcast mechanism in distributed shared caches. Microelectron. J. 118: 105286 (2021) - [j27]Jun Yin, Jun Han, Ruiqi Xie, Chenghao Wang, Xuyang Duan, Yitong Rong, Xiaoyang Zeng, Jun Tao:
MC-LSTM: Real-Time 3D Human Action Detection System for Intelligent Healthcare Applications. IEEE Trans. Biomed. Circuits Syst. 15(2): 259-269 (2021) - [j26]Yuanyuan Han, Tongde Li, Xu Cheng, Liang Wang, Jun Han, Yuanfu Zhao, Xiaoyang Zeng:
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2962-2975 (2021) - [j25]Chiyu Tan, Yan Li, Xu Cheng, Jun Han, Xiaoyang Zeng:
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 3044-3057 (2021) - [j24]Ruiqi Xie, Jun Yin, Jun Han:
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 5095-5107 (2021) - [j23]Keji Zhou, Chenyang Zhao, Jinbei Fang, Jingwen Jiang, Deyang Chen, Yujie Huang, Ming-e Jing, Jun Han, Haidong Tian, Xiankui Xiong, Qi Liu, Xiaoyong Xue, Xiaoyang Zeng:
An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2932-2936 (2021) - [c57]Xuyang Duan, Ruiqi Xie, Jun Han:
An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture. ASICON 2021: 1-4 - [c56]Xinyu Qin, Xudong Liu, Jun Han:
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC. ASICON 2021: 1-4 - [c55]Ruiqi Xie, Jun Han:
Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection. ASICON 2021: 1-4 - [c54]Jue Wang, Zhenyu Yang, Jiawei Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. A-SSCC 2021: 1-3 - [c53]Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori:
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. DATE 2021: 88-93 - [c52]Guozhu Xin, Yifan Zhao, Jun Han:
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning. ISCAS 2021: 1-5 - [c51]Zikang Zhou, Chao Fu, Ruiqi Xie, Jun Han:
A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations. MCSoC 2021: 164-170 - 2020
- [j22]Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng:
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2672-2684 (2020) - [j21]Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng:
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1619-1623 (2020) - [j20]Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng:
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1089-1093 (2020) - [j19]Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng:
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1423-1434 (2020) - [c50]Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng:
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC 2020: 1-6 - [c49]Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng:
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS 2020: 1-5 - [c48]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS 2020: 1-5 - [c47]Jun Yin, Jun Han, Xiaodong Zhang:
An Optimization Toolchain Design of Deep Learning Deployment Based on Heterogeneous Computing Platform. WCSP 2020: 631-635
2010 – 2019
- 2019
- [j18]Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng:
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2052-2056 (2019) - [c46]Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng:
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. ASICON 2019: 1-3 - [c45]Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng:
A Skeleton-based Action Recognition System for Medical Condition Detection. BioCAS 2019: 1-4 - 2018
- [j17]Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng:
Countering power analysis attacks by exploiting characteristics of multicore processors. IEICE Electron. Express 15(7): 20180084 (2018) - [c44]Bingyi Zhang, Xin Li, Jun Han, Xiaoyang Zeng:
MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. DSP 2018: 1-5 - [c43]Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng:
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. ISOCC 2018: 123-124 - 2017
- [j16]Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu:
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14(18): 20170768 (2017) - [c42]Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng:
FPGA-based efficient implementation of SURF algorithm. ASICON 2017: 315-318 - [c41]Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng:
A configurable nonlinear operation unit for neural network accelerator. ASICON 2017: 319-322 - [c40]Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng:
Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm. ASICON 2017: 561-564 - [c39]Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng:
A high utilization FPGA-based accelerator for variable-scale convolutional neural network. ASICON 2017: 944-947 - [c38]Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON 2017: 953-956 - [c37]Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng:
Instruction set extension and hardware acceleration for SVM application toward a vector processor. ISOCC 2017: 42-43 - 2016
- [j15]Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng:
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 984-988 (2016) - [c36]Shan Huang, Jun Han, Xin Li, Zongxian Yang, Xiaoyang Zeng:
A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. BioCAS 2016: 344-347 - [c35]Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng:
Cryptographie coprocessor design for IoT sensor nodes. ISOCC 2016: 37-38 - 2015
- [j14]Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng:
A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. IEEE Signal Process. Lett. 22(8): 1118-1122 (2015) - [j13]Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng:
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs 62-II(2): 119-123 (2015) - [j12]Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng:
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1372-1381 (2015) - [j11]Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 692-701 (2015) - [j10]Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu:
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - [c34]Tianchan Guan, Jun Han, Xiaoyang Zeng:
Exploration for energy-efficient ECC decoder of WBAN. ASICON 2015: 1-4 - [c33]Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng:
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON 2015: 1-4 - [c32]Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
Motion artifact removal based on ICA for ambulatory ECG monitoring. ASICON 2015: 1-4 - [c31]Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng:
A SIMD multiplier-accumulator design for pairing cryptography. ASICON 2015: 1-4 - [c30]Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON 2015: 1-4 - [c29]Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
A low-cost SoC implementation of AES algorithm for bio-signals. ASICON 2015: 1-4 - [c28]Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng:
A configurable SoC design for information security. ASICON 2015: 1-4 - 2014
- [j9]Yi Li, Liang Wen, Yuejun Zhang, Xu Cheng, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. IEICE Electron. Express 11(3): 20130992 (2014) - [j8]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014) - [j7]Renfeng Dou, Jun Han, Yifan Bo, Zhiyi Yu, Xiaoyang Zeng:
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2245-2255 (2014) - [c27]Mengyuan Chen, Jun Han, Yicheng Zhang, Yao Zou, Yi Li, Xiaoyang Zeng:
An error-resilient wavelet-based ECG processor under voltage overscaling. BioCAS 2014: 628-631 - 2013
- [j6]Pengjun Wang, Yuejun Zhang, Jun Han, Zhiyi Yu, Yibo Fan, Zhang Zhang:
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(5): 963-970 (2013) - [j5]Yao Zou, Jun Han, Xinqian Weng, Xiaoyang Zeng:
An Ultra-Low Power QRS Complex Detection Algorithm Based on Down-Sampling Wavelet Transform. IEEE Signal Process. Lett. 20(5): 515-518 (2013) - [j4]Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng:
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2325-2330 (2013) - [c26]Yifan Bo, Renfeng Dou, Jun Han, Xiaoyang Zeng:
A hardware-efficient variable-length FFT processor for low-power applications. APSIPA 2013: 1-4 - [c25]Mengyuan Chen, Jun Han, Dabin Fang, Yao Zou, Xiaoyang Zeng:
An ultra low-power and area-efficient baseband processor for WBAN transmitter. APSIPA 2013: 1-4 - [c24]Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng:
Design of a high throughput configurable variable-length FFT processor based on switch network architecture. ASICON 2013: 1-4 - [c23]Tianchan Guan, Jun Han, Xiaoyang Zeng:
Highly flexible WBAN transmit-receive system based on USRP. ASICON 2013: 1-4 - [c22]Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng:
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. ASICON 2013: 1-4 - [c21]Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng:
Low power design for FIR filter. ASICON 2013: 1-4 - [c20]Yi Li, Xu Cheng, Yicheng Zhang, Weijing Shi, Jun Han, Xiaoyang Zeng:
A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. BioCAS 2013: 154-157 - [c19]Shuai Wang, Jun Han, Yang Li, Yifan Bo, Xiaoyang Zeng:
A 920MHz quad-core cryptography processor accelerating parallel task processing of public-key algorithms. CICC 2013: 1-4 - [c18]Dabin Fang, Huikai Li, Jun Han, Xiaoyang Zeng:
Robustness Analysis of Mesh-Based Network-on-Chip Architecture under Flooding-Based Denial of Service Attacks. NAS 2013: 178-186 - 2012
- [j3]Jun Han, Xingxing Zhang, Yi Li, Baoyu Xiong, Yuejun Zhang, Zhang Zhang, Zhiyi Yu, Xu Cheng, Xiaoyang Zeng:
A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. IEICE Electron. Express 9(16): 1355-1361 (2012) - [j2]Weina Zhou, Lin Dai, Yao Zou, Xiaoyang Zeng, Jun Han:
A High Speed Reconfigurable Face Detection Architecture Based on AdaBoost Cascade Algorithm. IEICE Trans. Inf. Syst. 95-D(2): 383-391 (2012) - [j1]Yuli Zhang, Jun Han, Xinqian Weng, Zhongzhu He, Xiaoyang Zeng:
Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm. IEICE Trans. Electron. 95-C(8): 1415-1426 (2012) - [c17]Yifan Bo, Jun Han, Yao Zou, Xiaoyang Zeng:
A low power ASIP for precision configurable FFT processing. APSIPA 2012: 1-4 - 2011
- [c16]Junbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng:
Analysis of adaptive support-weight based stereo matching for hardware realization. ASICON 2011: 51-54 - [c15]Yang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng:
A NoC-based multi-core architecture for IEEE 802.11i CCMP. ASICON 2011: 196-199 - [c14]Baoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Design of a single-ended cell based 65nm 32×32b 4R2W register file. ASICON 2011: 311-314 - [c13]Jun Han, Xingxing Zhang, Baoyu Xiong, Zhiyi Yu, Xiaoyang Zeng:
A control scheme for a 65nm 32×32b 4-read 2-write register file. ASICON 2011: 739-742 - [c12]Shuai Wang, Yang Li, Junbao Liu, Jun Han, Xiaoyang Zeng:
A security processor based on MIPS 4KE architecture. ASICON 2011: 751-754 - 2010
- [c11]Yulong Zhang, Xubin Chen, Wenhua Fan, Jun Han, Xiaoyang Zeng:
Robust and reliable frame synchronization method for DVB-S2 system. WTS 2010: 1-5 - [c10]Yulong Zhang, Jialin Cao, Chuan Wu, Jun Han, Xiaoyang Zeng:
Optimized digital automatic gain control for DVB-S2 system. WTS 2010: 1-5
2000 – 2009
- 2009
- [c9]Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu:
A multi-task-oriented security processing architecture with powerful extensibility. ASP-DAC 2009: 133-134 - 2008
- [c8]Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao:
A low-cost cryptographic processor for security embedded system. ASP-DAC 2008: 113-114 - [c7]Li Qing, Xiaoyang Zeng, Chuan Wu, Yulong Zhang, Yunsong Deng, Jun Han:
Optimal frame synchronization for DVB-S2. ISCAS 2008: 956-959 - [c6]Daxian Yun, Yanjie Peng, Jun Han, Xiaoyang Zeng:
Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. ISCAS 2008: 2490-2493 - [c5]Liang Li, Jun Han, Xiaoyang Zeng, Jia Zhao:
A full-custom design of AES SubByte module with signal independent power consumption. ISCAS 2008: 3302-3305 - 2007
- [c4]Jing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng:
An Energy-Proportion Synchronization Method for IR-UWB Communications. ISCAS 2007: 2578-2581 - [c3]Yehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao:
A Low-cost and High-performance SoC Design for OMA DRM2 Applications. ISCAS 2007: 3510-3513 - [c2]Jia Zhao, Jun Han, Xiaoyang Zeng, Yunsong Deng:
Two-dimensional Parity-based Concurrent Error Detection Method for AES Algorithm against Differential Fault Attack and its VLSI Implementation. SiPS 2007: 151-156 - 2006
- [c1]Min Wu, Xiaoyang Zeng, Jun Han, Yongyi Wu, Yibo Fan:
A high-performance platform-based SoC for information security. ASP-DAC 2006: 122-123
Coauthor Index
[j47] [j46] [j44] [j43] [j42] [j41] [c73] [c68] [j36] [j35] [j34] [c63] [c60] [c59] [c58] [j31] [j30] [j29] [j27] [j26] [j25] [j23] [c54] [c53] [j22] [j21] [j20] [j19] [c50] [c49] [c48] [j18] [c46] [c45] [j17] [c44] [c43] [j16] [c42] [c41] [c40] [c39] [c38] [c37] [j15] [c36] [c35] [j14] [j13] [j12] [j11] [j10] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [j9] [j8] [j7] [c27] [j5] [j4] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [j3] [j2] [j1] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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