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2020 – today
- 2022
[c5]Ming Yao, Yu Bai, Wei Du, Xuejun Zhang, Heng Quan, Fuli Cai, Hongwei Kang:
Multi-Level Spatiotemporal Network for Video Summarization. ACM Multimedia 2022: 790-798- 2020
- [j2]Xiaoqiang Zhao, Shaoya Ren, Heng Quan, Qiang Gao
:
Routing Protocol for Heterogeneous Wireless Sensor Networks Based on a Modified Grey Wolf Optimizer. Sensors 20(3): 820 (2020)
2010 – 2019
- 2014
- [j1]Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng:
A 16-Core Processor With Shared-Memory and Message-Passing Communications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1081-1094 (2014) - 2013
- [c4]Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu:
A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. ISSCC 2013: 56-57 - 2012
- [c3]Yan Ying, Kaidi You, Liyang Zhou, Heng Quan, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. ISCAS 2012: 2609-2612 - [c2]Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng:
An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. ISSCC 2012: 64-66 - 2011
- [c1]Yueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu:
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. ASICON 2011: 267-270
Coauthor Index
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