"A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using ..."

Jiawei Wang et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TCSII.2023.3335987

access: closed

type: Journal Article

metadata version: 2024-04-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/WangGCWLHZ24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/WangGCWLHZ24
Jiawei Wang, Zhao Gao, Xu Cheng, Jue Wang, Zhen Li, Jun Han, Xiaoyang Zeng:
A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1859-1863 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.