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ORCID13th ASICON 2019: Chongqing, China
- 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. IEEE 2019, ISBN 978-1-7281-0735-6
- Wei Liu, Weilin Cong, Chengyu Hu, Peng Lu, Jinmei Lai:
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs. 1-4 - Cong Lai, Guangyu Wang, Qingyu Yang, Hongbin Sun:
Efficient Photometric Alignment for Around View Monitor System. 1-4 - Xiaoxu Kang, Xiaolan Zhong, Ming Li:
Development and Optimization of Contact Module Process for Micro-Bridge Structure based MEMS/Sensor Application. 1-4 - Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng:
Learning Sparse Patterns in Deep Neural Networks. 1-4 - Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren:
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. 1-4 - Lei Liu, Yao Yao
, Meng-Qi Wen, Yue Li, David Wei Zhang:
A pn-Coupled Superjunction IGBT for High Switching Speed. 1-4 - Lin Li, Qiu Huang, Jianhao Hu, Jienan Chen:
A Novel Signed Bit-serial Fixed-point Accumulator with Configurable Overflow-Protection Precision. 1-4 - Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo:
High-speed Classification of AER Data Based on a Low-cost Hardware System. 1-4 - Kazuhiko Endo:
Post-Si Nano Device Technology. 1 - Qiuhong Ying, Lun-Yao Wang, Zhufei Chu, Yinshui Xia:
Area Optimization of MPRM Circuits Using Approximate Computing. 1-4 - Ming Zhang, Nicolas Llaser:
High Intensity Focused Ultrasound for Noninvasive Medical Applications. 1-4 - Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang:
A New Approximate Multiplier Design for Digital Signal Processing. 1-4 - Takuya Asuke, Ryo Kishida, Jun Furuta, Kazutoshi Kobayashi:
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. 1-4 - Jun Qiao, Xiao Wang, Yaohong Zhao:
Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAs. 1-3 - Yu-Cheng Su, Kang-Yu Chang, Yu-Tung Chin, Chia-Wen Chang, Shyh-Jye Jou:
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays. 1-4 - Yangyang Chang, Gerald E. Sobelman, Xiaofang Zhou:
Genetic Architecture Search for Binarized Neural Networks. 1-4 - Xiao Shi, Jinlong Yan, Hao Yan, Jiajia Zhang, Jinxin Wang, Longxing Shi, Lei He:
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling. 1-4 - Huashu Wang, Wei Ma, Zhiming Xiao, Wei-Chih Cheng, Liang Wang, Fanming Zeng, Hongyu Yu, Weibo Hu:
The Design and Performance Comparison of Wide Bandwidth LNA with Three Different Kinds of Technologies. 1-4 - Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng:
Parallel Global Placement on CPU via Parallel Reduction. 1-4 - Abdulraqeb Abdullah Saeed Abdo, Jie Ling, Pinghua Chen:
Architecture considerations of LTE/WCDMA wideband power amplifier for efficiency improvement. 1-4 - Xiaozhi Kang, Xiaoxu Kang, Zijian Zhao, Jingxiu Ding, Yi Hu, Dapeng Xu, Qingqing Sun, David Wei Zhang:
Low-Dropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit. 1-4 - Min Zhang, Peng Huang, Yizhou Zhang, Yachen Xiang, Runze Han, Lifeng Liu, Xiaoyan Liu, Jinfeng Kang:
FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network. 1-4 - Xian Zhang, Yong Xu:
High precision low power CMOS bandgap for RFID. 1-4 - Muchan Li, Pei Peng, Zhongzheng Tian, Liming Ren, Yunyi Fu:
Adsorbates on Multilayer Graphene Surface: Morphology, Distribution and Electrical Properties. 1-4 - Yulong Zhu, Futian Liang, Xinzhe Wang, Bo Feng, Chenxi Zhu, Ge Jin:
An ASIC for Discriminating Single Photon Detector Signal of High-Speed Quantum Key Distribution System. 1-4 - Yan-Ming Li, Xiao-Xiao Wang, Xiao-Li Xi, Jian Sun, Zhong-Hui Chen:
A FT Trimming Circuit Based on EPROM and Pin Multiplexing. 1-4 - Riho Aoki, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Yuto Sasaki, Kosuke Machida, Takayuki Nakatani, Jianlong Wang, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi:
Evaluation of Null Method for Operational Amplifier Short-Time Testing. 1-4 - Xiaotian Zhang, Pengjun Wang, Yunfei Yu, Yuejun Zhang, Shunxin Ye:
A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback. 1-4 - Ran Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao:
Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters. 1-4 - Lintao Li, Jiangyi Shi, Zhixiong Di:
High Parallel VLSI Architecture Design of BPC in JPEG2000. 1-4 - Junning Jiang, Liang Cai, Feng Dong, Kehua Yu, Ke Chen, Wei Qu, Jianfei Jiang:
Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture. 1-4 - Yue Shi, Jiawen Wang, Jianwen Cao, Zekun Zhou:
An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency. 1-4 - Fuqiang Liu, Mingfeng Chen, Heng Ma, Zhiliang Hong:
Dual-Loop-Controlled AC-Coupling 100MHz Bandwidth Envelope Tracking Modulator for 5G RF Power Amplifier. 1-4 - Hao Li, Hongmei Yu, Dongsheng Liu, Peng Liu, Bo Liu:
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module. 1-4 - Lili Zhang, Wen Kuang:
Research and Implementation of TPC Coding In High Bit Rate Telemetry System. 1-4 - Mingfeng Chen, Fuqiang Liu, Heng Ma, Zhiliang Hong:
High-Bandwidth Wide-Output-Swing Linear Amplifier for LTE-100MHz Envelope Tracking. 1-4 - Jiafeng Liu, Zhiyin Lu, Xie Xie, Jian Wang, Jinmei Lai:
An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform. 1-4 - Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun:
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. 1-4 - Yu Ma, Linfeng Zheng, Pingqiang Zhou:
CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM. 1-4 - Yi Zhang, Xiaoshan He, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Enhanced Recursive Residual Network for Single Image Super-Resolution. 1-4 - Junwei Yang, Weiwei Shi, Zhiyu Huang, Yuan Xu, Yanghao Zheng, Xuanbin Fang:
A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application. 1-4 - Toufik Sadi, Oves Badami, Vihar P. Georgiev, Jie Ding, Asen Asenov:
Advanced Simulation of RRAM Memory Cells. 1-4 - Ang Hu, Dongsheng Liu, Zirui Jin, Cong Zhang, Ke-feng Zhang, Lan-qi Liu:
RF Transceiver System Design: From Protocols to Specifications. 1-4 - Chenxi Zhu, Futian Liang, Bo Feng, Xinzhe Wang, Yulong Zhu, Chengzhi Peng:
An adjustable amplitude and pulse-width laser modulation driver with active feedback for QKD experiments. 1-4 - Pengfeng Zhang, Jianping Hu:
Dual-Threshold Independent-Gate TFET with Tri-side Tunneling. 1-4 - Danyang Yang, Zibin Dai, Wei Li, Tao Chen:
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit. 1-4 - Yang Yang Peng, Ping Li, Yang Li:
Reconfigurable RF Power Amplifier in 5G/4G with RF-SOI CMOS. 1-4 - Haoyang Zhou, Wei Li, Tao Wang, Jiao Ye, Chuangguo Wang:
A Class-F3 VCO with 104% Ultra-Wide Band Tuning Range and -125dBc/Hz Phase Noise. 1-4 - Zhimei Cai, Zhiyong Han, Ming Tian, Changfeng Wang, Xiaoming Hu, Ran Cheng, Yi Zhao:
Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology. 1-4 - Yufei Sun, Yanzhao Ma, Kai Cui, Xiaoya Fan:
A Low-Power Comparator-Less Relaxation Oscillator. 1-4 - Ruiqiang Song, Jinjin Shao, Bin Liang, Yaqing Chi, Jianjun Chen:
A Single-Event Upset Evaluation Approach Using Ion-Induced Sensitive Area. 1-4 - Wentao Lv, Xiaokang Niu, Lianming Li:
A 60GHz Digitally-Controlled Differential Reflection-type Phase Shifter in 65-nm CMOS with Low Phase Error. 1-4 - Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min:
Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing. 1-4 - Xing Zhou, Siau Ben Chiah, Binit Syamal, Kenneth Eng-Kian Lee:
Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits. 1-4 - Xinyuan Qu, Zhihong Huang, Ning Mao, Yu Xu, Gang Cai, Zhen Fang:
A Grain-Adaptive Computing Structure for FPGA CNN Acceleration. 1-4 - Zhongshan Zheng, Zhentao Li, Bo Li, Jiajun Luo, Zhengsheng Han:
Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells. 1-3 - Zirui Jin, Ang Hu, Zilong Liu, Dongsheng Liu:
A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical Applications. 1-4 - Yiran Sun, Ju Zhou, Shiying Zhang, Xuexiang Wang:
Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm. 1-4 - Lun Zhang, Weikang Qian, Hai-Bao Chen:
Area-Efficient Parallel Stochastic Computing with Shared Weighted Binary Generator. 1-4 - Horng-Chih Lin, Yu-An Huang:
A Platform with Exquisite Film Profile Engineering in Oxide-Based Thin-Film Transistors for More-than-Moore Applications. 1-3 - Makoto Nagata:
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. 1-4 - Chongzhou Fang, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Automatic Hardware Design Tool Based on Reusing Transformation. 1-4 - Peng Sun, Yun Li, Yao Yao, Peng-Fei Wang:
Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm. 1-4 - Suwen Song, Jing Tian, Jun Lin, Zhongfeng Wang:
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes. 1-4 - Yu Ma, Dingcheng Jia, Huifan Zhang, Ruoyu Wang, Pingqiang Zhou:
A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays. 1-4 - Tao Wang, Wei Li, Haoyang Zhou, Jiao Ye, Yuanyuan Xu:
An 8-12GHz Class-F3 VCO with Multi-LC Tank in 28nm CMOS. 1-4 - Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo:
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. 1-4 - Xiangnan Song, Shiying Zhang, Ju Zhou, Xuexiang Wang:
A Variation Aware Register Clustering Methodology in Near-Threshold Region. 1-4 - Sheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai:
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. 1-4 - Weiiie Xu, Yudi Zhao, Peng Huang, Xiaoyan Liu, Jinfeng Kang:
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model. 1-4 - Yuan Cheng, Ngai Wong, Xiong Liu, Leibin Ni, Hai-Bao Chen, Hao Yu:
A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks. 1-4 - Xuefeng Ye, Duoduo Zeng, Xiangliang Jin, Yang Wang:
A Low-Temperature-Coefficient and High-PSRR Bandgap Reference for Readout Circuit of SPAD. 1-4 - Ziyun He, Shaoquan Liao, Zixin Wang, Jianping Guo:
A Power-Area-Efficient Low-Dropout Regulator With Enhanced Buffer Impedance Attenuation. 1-4 - Cong Liu, MouFu Kong, Hanzhi Chen, Bo Yi, Bingke Zhang, Xingbi Chen:
Simulation Study on Novel High Voltage Transient Voltage Suppression Diodes. 1-4 - Ye Yuan, Song Ma, Yuhua Cheng:
Circuit Design Challenges of ADC for the Application in Multiple Physiological Parameters Detection System. 1-4 - Jinfeng Kang, Peng Huang, Runze Han, Yachen Xiang, Xiaole Cui, Xiaoyan Liu:
Flash-based Computing in-Memory Scheme for IOT. 1-4 - Wenjie Huang, Qihui Zhang, Jing Li, Zhong Zhang, Heng Deng, Ning Ning, Qi Yu:
A Calibration Technique for Two-Step Single-Slope Analog-to-Digital Converter. 1-4 - Haoran Gong, Yunhao Fu, Ning Ding, Jiaqi Jiang, Yuchun Chang:
A Readout Circuit of Microchannel Plate Light Detector in 0.13um CMOS Technology. 1-4 - Jiahao Lu, Xianghua Luo, Dongsheng Liu, Peng Liu, Bo Liu:
A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron. 1-4 - Hanze Zheng, Yinshui Xia:
Dual-Source Energy Cooperative Harvesting Circuit with Single Inductor. 1-4 - Haruo Kobayashi, Kosuke Machida, Yuto Sasaki, Yusuke Osawa, Pengfei Zhang, Lei Sha, Yuki Ozawa, Anna Kuwana:
Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types. 1-4 - Jinsong Wei, Jilin Zhang, Xumeng Zhang, Zuheng Wu, Chunmeng Dou, Tuo Shi, Hong Chen, Qi Liu:
An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron. 1-4 - Haosheng Zeng, Hong Zhang, Jianping Guo:
A CMOS Half-Bridge GaN Driver with 6-30V Input Voltage Range and 5.4ns Propagation Delay. 1-4 - Dehong Lv, Heng Ma, Fuqiang Liu, Zhiliang Hong:
A curvature corrected bandgap reference with mismatch cancelling and noise reduction. 1-4 - Qiao Yuan, Huajian Zhang, Yukun Song, Chongyang Li, Xueyi Liu, Zheng Yan:
The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor. 1-4 - Hejia Cai, Yan Hu, Zhiliang Hong:
A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control. 1-4 - Jinfou Xie, Shixian Li, Yun Chen, Qichen Zhang, Xiaoyang Zeng:
High throughput multi-code LDPC encoder for CCSDS standard. 1-4 - Cristine Jin Estrada, Chen Xu, Mansun Chan:
Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor. 1-4 - Jie Li, Liyi Xiao, Hongchen Li, Lulu Liao, Chenxu Wang:
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network. 1-4 - Yifei Wang, Xiaofei Wang, Yuekang Guo, Ting Jin:
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter. 1-4 - Liang Pang, Yifan Chai, Mengyun Yao, Yaqing Men, Xuexiang Wang, Longxing Shi:
An Accurate and Efficient Yield Analysis for SRAM dynamic metrics Using Differential Evolution Algorithm. 1-4 - Liang Qi, Sai-Weng Sin, Rui Paulo Martins:
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. 1-4 - Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling:
A Fast Reduction Method for Path Process Variations Without Time-Consuming Training. 1-4 - Zhenghua Gu, Wenqin Wan, Chang Wu:
Latency Minimal Scheduling with Maximum Instruction Parallelism. 1-4 - Chun Zhao, Ce Zhou Zhao, Tian Shi Zhao:
Solution Processed Metal Oxide in Emerging Electronic Devices. 1-4 - Jia-Qiang Li, Li-Yi Xiao, Liu He, Hao-Tian Wu:
A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories. 1-4 - Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu:
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. 1-4 - Yalong Pang, Shuai Jiang, Lu-yuan Wang, Weiwei Liu, Ji-yang Yu, Yuehua Niu:
A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGA. 1-4 - Zekun Zhou, Zhengyang Jin, Jianwen Cao, Bo Zhang, Yue Shi:
An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck Converters. 1-4 - Xueyou Shi, Dahe Liu, Zhongjian Chen, Guangyi Chen, Shoudong Huang, Wengao Lu, Yacong Zhang:
A Low-Power Single-Slope based 14-bit Column-Level ADC for 384×288 Uncooled Infrared Imager. 1-4 - Ning Li, Wen-Yang Jiang, Blacksmith Wu, Kanyu Cao:
Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation. 1-4 - Qi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu:
An Area-Efficient Multi-Rate Digital Decimator. 1-4 - Minyuan Ye, Lei He, Gengsheng Chen:
A Coarse-to-fine Classification for Motion Blur Kernel Size Estimation with Cascaded Neural Networks. 1-4 - Junshang Li, Zishang He, Yajie Qin:
Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS. 1-4 - Yann Deval, Hervé Lapuyade, François Rivet:
Design of CMOS integrated circuits for radiation hardening and its application to space electronics. 1-4 - Siddharth Katare, Nagaveni Subramanya:
Configurable Hybrid Output Driver for GPIO with Wide Supply Voltage Range of 1.05V-3.70V. 1-3 - Zhiwei Zhao, Yuejun Zhang, Pengjun Wang, Huihong Zhang, Zhang Weishan:
Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance. 1-4 - Xinning Liu, Song Jia, Hanzun Zhang:
A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. 1-4 - Mengyuan Hua, Song Yang, Jin Wei, Zheyang Zheng, Jiabei He, Kevin J. Chen:
Reverse-Bias Stability and Reliability of Enhancement-mode GaN-based MIS-FET. 1-4 - Xiaoyu Zhang, Bin Liang, Ruiqiang Song:
Circuit-Level Soft Error Rate Evaluation Approach Considering Single-Event Multiple Transient. 1-4 - Junyao Wang, Hairui Wang, Bo Wang:
A 5-bit, 87-fs Step, Constant-Slope, Charge-Sharing-Based Encoding Digital-to-Time Converter in 130nm CMOS. 1-4 - Runsheng Wang, Zhe Zhang, Shaofeng Guo, Qingxue Wang, Dehuang Wu, Joddy Wang, Ru Huang:
OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits. 1-4 - Zhao Tuo, Tao Chen, Wei Li, Danyang Yang:
Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor. 1-4 - Pingshun Ma, Yongzhen Chen, Jiangfeng Wu:
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. 1-3 - Francis Balestra:
Nanoscale Devices for the end of the Roadmap. 1-4 - Xubo Song, Yuangang Wang, Zhihong Feng, Yuanjie Lv, Yamin Zhang, Lisen Zhang, Shixiong Liang, Xin Tan, Shaobo Dun, Dabao Yang, Zhirong Zhang:
GaN Schottky Diode Model for THz Multiplier Design with Consideration of Self-heating Effect. 1-3 - Huanlin Luo, Yunbo Liu, Hai Ren, Tiantian Zhang, Jian Wang, Jinmei Lai:
An FPGA-based log-structure Flash memory system for space exploration. 1-4 - Jian Gong, Zirun Zhao, Ziqing Wang, Yonghui Wu, Yong Cui:
A 20GS/s Track-and-Hold Amplifier based on InP DHBT Process. 1-4 - Koji Asami, Nene Kushita, Akemi Hatta, Minh Tri Tran, Yoshiro Tamura, Anna Kuwana, Haruo Kobayashi:
Analysis and Evaluation Method of RC Polyphase Filter. 1-4 - Xinpeng Xing, Pengyi Cao, Haigang Feng, Zhihua Wang:
A 0.9/1.8/2.4GHz-reconfigurable LNA with Inductor and Capacitor Tuning for IoT Application in 65nm CMOS. 1-4 - Chenglong Zou, Xin'an Wang, Boxing Xu, Yisong Kuang, Xiaoxin Cui:
Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System. 1-4 - Haruo Kobayashi, Nene Kushita, Minh Tri Tran, Koji Asami, Hao San, Anna Kuwana, Akemi Hatta:
Analog / Mixed-Signal / RF Circuits for Complex Signal Processing. 1-4 - Huimin Qian, Jianping Guo:
A 1.26-ps-FoM Output-Capacitorless LDO with Dual-Path Active-Feedback Frequency Compensation and Current-Reused Dynamic Biasing in 65-nm CMOS Technology. 1-4 - Jiqing Xu, Zhengjie Li, Yunbing Pang, Jian Wang, Gang Qu, Jinmei Lai:
Research on the impact of different benchmark circuits on the representative path in FPGAs. 1-3 - Songting Li, Lihu Chen, Yong Zhao:
One-channel Zero-IF Multi-mode GNSS Receiver with Self-adaptive Digitally-assisted Calibration. 1-4 - Benqing Guo, Haifeng Liu, Yao Wang, Jun Chen:
A 60 GHz single-to-differential LNA using slow-wave CPW and transformer coupling in 28 nm CMOS. 1-4 - Zhi-Yin Lu, Jia-Feng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jin-Mei Lai, Jian Wang:
A Low-delay Configurable Register for FPGA. 1-4 - Jingrui Ma, Qi-An Xu, Blacksmith Wu, Kanyu Cao:
Improved Model for ESD Failure Caused by Stressing No Connect Pin. 1-4 - Jiang-Lin Wei, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Nene Kushita, Takahiro Arai, Lei Sha, Anna Kuwana, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato:
High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm. 1-4 - Yu Ji, Li Ding, Jing Jin:
A High-Linear Digital-to-Phase Converter in 40nm CMOS. 1-4 - Ce Guo, Wayne Luk, Wenguang Xu:
Non-linear function evaluation reusing matrix-vector multipliers. 1-4 - Hongchen Li, Liyi Xiao, Jie Li, He Liu:
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology. 1-4 - Jianfu Zhang, Azrif Manut, Rui Gao, Mehzabeen Mehedi, Zhigang Ji, Weidong Zhang, John S. Marsland:
An assessment of RTN-induced threshold voltage jitter. 1-4 - Weijie You, Chang Wu:
An Efficient Accelerator for Sparse Convolutional Neural Networks. 1-4 - Yan Hu, Tao Wang, Zhiliang Hong:
The Digital Front End with Dual-box Digital Pre-distortion in All-digital Quadrature Transmitter. 1-4 - Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang:
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. 1-4 - Shogo Katayama, Noriyuki Oiwa, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Output Voltage Ripple Reduction with Nosie Spread Spectrum for Dual-Phase LLC Resonant Converter. 1-4 - Zongxia Guo, Kaihua Cao, Kewen Shi, Weisheng Zhao:
Ultra-low power consumption Spintronics Devices. 1-4 - Minh Tri Tran, Yifei Sun, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Overshoot Cancelation Based on Balanced Charge-Discharge Time Condition for Buck Converter in Mobile Applications. 1-4 - Xin Ming, Zhi-Wen Zhang, Ziwei Fan, Yao Qin, Yuan-Yuan Liu, Bo Zhang:
High Reliability GaN FET Gate Drivers for Next-generation Power Electronics Technology. 1-4 - Ruo-Lan Yu, Wei Liang, Jie Zhang, Yan Li, Wei-Wei Chen, Peng-Jun Wang:
An electro-optical full-subtractor using hybrid-integrated silicon-graphene waveguides. 1-4 - Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto:
Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model. 1-4 - Hao Jiang, Yang Fan, Xuan Zeng:
Scheduling Algorithm Based on System of Difference Constraints Using Network Flow. 1-4 - Yudai Abe, Shogo Katayama, Congbing Li, Anna Kuwana, Haruo Kobayashi:
Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System. 1-4 - Xinyue Zhang, Jiahao Song, Yuan Wang, Yawen Zhang, Zuodong Zhang, Runsheng Wang, Ru Huang:
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. 1-4 - Rongxin Chen, Bo Yi, MouFu Kong, Xingbi Chen:
Simulation Study of Trench IGBT with Diode-Clamped P-Well for High dI/dt and dV/dt Controllability. 1-4 - Chunlin Xu, Wei Ni, Yukun Song:
UVM-based Functional Coverage Driven AXI4-Stream Verification. 1-4 - Peiqing Han, Niansong Mei, Zhaofeng Zhang:
A UHF Semi-Passive RFID System with Photovoltaic/Thermoelectric Energy Harvesting for Wireless Sensor Networks. 1-4 - Ru Ding, Xuemei Tian, Guoqiang Bai, Guangda Su, Xingjun Wu:
Hardware Implementation of Convolutional Neural Network for Face Feature Extraction. 1-4 - Chunmei Hu, Zhenyang Zhang, Yang Guo, Jingyan Xu:
A Implementation for Built-in Self-Testing of RapidIO by JTAG. 1-4 - Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei:
BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead. 1-4 - Xinyu He, Xie Xie, Jinmei Lai, Jian Wang:
A Web-based Waveform Viewer for BR0101 Chip Testing Platform. 1-4 - Yunbing Pang, Jiqing Xu, Zhiyin Lu, Zhengjie Li, Yufan Zhang, Jinmei Lai:
Research on Area Modeling Methodology for FPGA Interconnect Circuits. 1-4 - Tao Wang, Hejia Cai, Yan Hu, Pan Xue, Zhiliang Hong:
A Compact Quadrature Doherty Digital Power Amplifier with Backoff Efficiency Enhancement. 1-3 - Yangsheng Wang, Yanyan Gao, Chong Feng, Nan Zhang:
A radiation resistant library based on DICE and fault-tolerant delay filtering techniques in CMOS 0.18μm technology. 1-4 - Manato Hirai, Shuhei Yamamoto, Hirotaka Arai, Anna Kuwana, Hiroshi Tanimoto, Yuji Gendai, Haruo Kobayashi:
Systematic Construction of Resistor Ladder Network for N-ary DACs. 1-4 - Jianguo Yang, Xiaowen Li, Qingting Ding, Xiaoyong Xue, Xiaoxin Xu, Qing Luo, Hangbing Lv, Ming Liu:
A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications. 1-4 - Mo Huang, Tingxu Hu, Xiu Yin Zhang, Yan Lu:
Design Considerations on Integrated Rectifiers with High Efficiency and Wide Input Power Range for RF Energy Harvesting. 1-4 - Yuehong Gang, Min Luo, Mingyu Wang:
An FPGA based verification platform for pipeline ADC digital calibration technology. 1-4 - Chun Cai, Hiromitsu Awano, Makoto Ikeda:
High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism. 1-4 - Wenqing Song, Yuxiang Fu, Qinyu Chen, Li Li, Chuan Zhang:
ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes. 1-4 - Chen-Hao Zhang, Yifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Multi-Phase Full/Half Wave Type Resonant Converters with Automatic Current Balance against Element Variation. 1-4 - Minh Tri Tran, Yifei Sun, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter. 1-4 - Peng Bo, Jin Xiang-Liang:
Analysis and Optimal Design of a New Single-Photon Memristor. 1-4 - Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. 1-4 - Timothy Dunlap, Gang Qu, Jinmei Lai:
A Polymorphic Circuit Interoperability Framework. 1-4 - Yu Ma, Dingcheng Jia, Wei Gao, Pingqiang Zhou:
Addressing Aging Issues in Heterogeneous Three-Dimensional Integrated Circuits. 1-4 - Yuan Xie, Luchang Ding, Aaron Zhou, Gengsheng Chen:
An Optimized Face Recognition for Edge Computing. 1-4 - Yuqing Ren, Weihong Xu, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Efficient Belief Propagation List Decoding of Polar Codes. 1-4 - Dishan Jing, Hai-Bao Chen:
SVM Based Network Intrusion Detection for the UNSW-NB15 Dataset. 1-4 - Yuto Tsukita, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi:
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. 1-4 - Minoru Fujishima:
Ultrahigh-Speed One-Chip CMOS Transceiver with 300-GHz Band. 1-4 - Guangqiu Lv, Wei Li, Tao Chen, Longmei Nan:
Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel. 1-4 - Zhigang Li, Xiaofei Wang, Jing Jin:
A 0.0558-mm2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS. 1-4 - Danqing Wu, Shilin Yan, Haodi Tang, Yu Wang, Jiayun Feng, Xianwu Hu, Jiaxin Cao, Yufeng Xie:
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme. 1-4 - Longheng Luo, Xingchen Shen, Jianguo Diao, Fan Ye, Junyan Ren:
A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC. 1-4 - Anna Kuwana, Jun-Ichi Matsuda, Haruo Kobayashi:
Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific On-Resistance. 1-4 - Dong Wei, Jincheng Zhang, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 22-40.5 GHz UWB LNA Design in 0.15um GaAs. 1-4 - Alan C. Seabaugh, Paolo Paletti, Anwesha Palit, Karla González-Serrano, Pratyush Pandey:
Dynamics of Ferroelectric and Ionic Memories: Physics and Applications. 1-4 - Xiaoyan Liu, Wangyong Chen, Linlin Cai, Gang Du, Xing Zhang:
Self-heating Induced Variability and Reliability in Advanced Logic Devices and Circuits. 1-4 - Ke Yang, Shaoyi Peng, Sheldon X.-D. Tan, Hai-Bao Chen:
Multi-Thread Assembling for Fast FEM Power Delivery DC Integrity Analysis. 1-4 - Tingrui Zhang, Siyu Chen, Shuwu Wei, Jienan Chen:
A Fast Signal Integrity Design Model of Printed Circuit Board based on Monte-Carlo Tree. 1-4 - Minh Tri Tran, Nene Kushita, Anna Kuwana, Haruo Kobayashi:
Flat Pass-Band Method with Two RC Band-Stop Filters for 4-Stage Passive RC Polyphase Filter in Low-IF Receiver Systems. 1-4 - Jinghao Ye, Masao Yanagisawa, Youhua Shi:
An Adder-Segmentation-based FIR for High Speed Signal Processing. 1-4 - Lingjuan Wu, Wenqian Zhao, Dunshan Yu:
Designing a 3D Graphics Processor for Mobile Applications. 1-4 - Yongsheng Wang, Anyi Wang, Lei Li, Chengxin Zhao:
A Micro Power High Precision Sigma-Delta ADC with Adjustable Decimation Ratio. 1-4 - Yongzhen Chen, Jiangfeng Wu:
High Linear Ring Amplifier Design with Analysis on Settling Procedures. 1-4 - Hao Sun, Jun Fu, Wenpu Cui, Tianling Ren, Linlin Liu, Wei Zhou, Quan Wang, Ao Guo:
Scalable Modeling for the CPW Gap Discontinuity at Frequency up to 150 GHz. 1-3 - Yichen Wang, Lunyao Wang:
Power optimization for FPRM logic using approximate computing technique. 1-4 - Conghui Zhao, Yingjian Yan, Wei Li:
An efficient ASIC Implementation of QARMA Lightweight Algorithm. 1-4 - Minhao Yang, Shih-Chii Liu, Mingoo Seok, Christian C. Enz:
Ultra-Low-Power Intelligent Acoustic Sensing using Cochlea-Inspired Feature Extraction and DNN Classification. 1-4 - Chung Fai Au-Yeung, Yiu Kei Li:
A CMOS Random Number Generator with Noise-Coupled Voltage-Controlled Oscillators. 1-4 - Li Ming, Zeng Zhi, Wei Hongtao:
A design of a wideband balanced limited low noise amplifier. 1-3 - Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. 1-4 - Wenbin He, Fan Ye, Junyan Ren:
A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology. 594-597 - Zhenhao Ji, Yahui Ji, Bolei Wang, Feifei Gao, Huizheng Wang, Chuan Zhang:
A New Uplink Channel Estimation Architecture for Massive MIMO Systems with PDMA. 1-4 - Yufeng Xu, Yi Guo, Shinji Kimura:
Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error Compensation. 1-4 - Shengkai Wang, Jilong Hao, Nannan You, Yun Bai, Xinyu Liu:
Rapid Growth of SiO2 on SiC with Low Ditusing High Pressure Microwave Oxygen Plasma. 1-4 - Xin Si, He Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, Shyh-Shyuan Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu:
Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. 1-4 - Yaochen Sheng, Xinyu Chen, Fuyou Liao, Jianan Deng, Jing Wan, Wenzhong Bao:
Graphene Top-gated Mos2 Phototransistors. 1-3 - Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen, Yi Kang, Feng Wu:
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN. 1-4 - Xilin Liu, Milin Zhang, Han Hao, Andrew G. Richardson, Timothy H. Lucas, Jan Van der Spiegel:
Wireless Sensor Brain Machine Interfaces for Closed-loop Neuroscience Studies. 1-4 - Haiming Zhang, Pengjun Wang, Yuejun Zhang, Yunfei Yu:
Design of Aging Detection Sensor Based on Voltage Comparison. 1-3 - Tianxiang Wu, Jincheng Zhang, Dong Wei, Lihe Nie, Yuting Yao, Shunli Ma, Junyan Ren:
A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication. 1-4 - Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa:
Switching of 3300V Scaled IGBT by 5V Gate Drive. 1-3 - Xie Xie, Qinghua Duan, Jiafeng Liu, Jian Wang, Jinmei Lai:
Design and implementation of Serial ATA pbysical layer on FPGA. 1-4 - Shiyu Wang, Md. Zakir Hossain, Takaaki Suzuki, Kazuo Shinozuka, Natsuhiko Shimizu, Shunya Kitada, Ryo Ichige, Anna Kuwana, Haruo Kobayashi:
Graphene Biosensor for Saliva Protein Adsorption. 1-4 - Jun Huang, MouFu Kong, Xingbi Chen:
A Low On-state Voltage and Large Current Capability Thin SOI-LIGBT with Trench NMOS. 1-4 - Baicheng Liu, Song Chen, Yi Kang, Feng Wu:
An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network. 1-4 - Peng Zou, Xiqiong Bai, Yingjie Wu, Lifeng Wu, Jianli Chen:
An Effective Detailed Routing Algorithm Considering Advanced VLSI Technologies. 1-4 - Yafei Li, Kuizhi Mei, Xiao Wang, Zeng Zhang, Hejie Yu:
Collaborative Implementation of Hardware-Oriented GBDT Compress Algorithm Based on DSP+FPGA. 1-4 - Yifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Pulse Coding Control Switching Converter with Adjustable Conversion Voltage Ratio Notch Frequency Generation in Noise Spectrum. 1-4 - Xuemei Fan, Rujin Wang, Qin Zeng, Hao Liu, Shengli Lu:
A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection. 1-4 - Jintao Li, Yanhan Zeng, Hailong Wu, Ruguo Li, Jun Zhang, Hong-Zhou Tan:
Performance optimization for LDO regulator based on the differential evolution. 1-4 - Marco Lanuzza, Raffaele De Rose, Esteban Garzón, Felice Crupi:
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. 1-4 - Yunhao Xu, Yingjie Lao, Weiqiang Liu, Chuan Zhang:
Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUF. 1-4 - Liang Wen, Yu Liu, Wei Mo, Jing Zhang, Shiqian Qi, Jianping Lv, Yuejun Zhang:
A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor. 1-4 - Sujuan Liu, Lili Zheng, Lei Liu, Qianjin Lin:
MMV Subspace Pursuit (M-SP) Algorithm for Joint Sparse Multiple Measurement Vectors Recovery. 1-4 - Luchang Ding, Zhize Huang, Gengsheng Chen:
An FPGA Implementation of GCN with Sparse Adjacency Matrix. 1-4 - Bo Chen, Pengjun Wang, Gang Li:
An Obfuscated Challenge Design for APUF to Resist Machine Learning Attacks. 1-4 - Joddy Wang, Frank Lee:
Advanced Reliability-Aware Verification for Robust Circuit Design. 1-4 - Houren Ji, Yifei Shen, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Flexible and Adaptive Path Splitting of Simplified Successive Cancellation List Polar Decoding. 1-4 - Tianyuan Tang, Ping Luo, Chengda Deng, Qiang Wang, Liao Zhang, Bo Zhang:
An Optimal Designed Compensator for PSR Flyback Converters Based on Genetic Algorithm. 1-4 - Zhiyong Chen, Weiwei Shi, Guoqiang Xiong, Junwei Yang, Yuan Xu:
A 63.3ps TDC Measurement System Based on FPGA for Pulsed Laser Ranging. 1-4 - Kaiwen Lu, Fengze Yan, Xingjie Liu, Dongsheng Liu, Peng Liu, Bo Liu:
Novel smart card SoC memory architecture based on embedded STT-MRAM. 1-4 - Steve S. Chung:
The Advances of OTP Memory for Embedded Applications in HKMG Generation and Beyond. 1-4 - Hongwei Tang, Fuyou Liao, Xinzhi Zhang, Jianan Deng, Jing Wan, Wenzhong Bao:
Mos2 transistor gated by PMMA-based electrolyte for sub-1 V operation. 1-4 - Ziwei Zhao, Fei Wang, Qi Ni:
An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points. 1-4 - Shoudong Huang, Wengao Lu, Ye Zhou, Shanzhe Yu, Yacong Zhang, Xueyou Shi, Zhongjian Chen:
An Automatic Slope-Calibrated Ramp Generator for Single-Slope ADCs. 1-4 - Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng:
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. 1-4 - Jian Chen, Wenfeng Zhao, Yajun Ha:
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing. 1-4 - Xitao Zheng, Mingcheng Zhu, Yuan Xu, Yutong Li:
An FPGA based Parallel Implementation for Point Cloud Neural Network. 1-4 - Caidie Cheng, Teng Zhang, Chang Liu, Jiadi Zhu, Liying Xu, Xiaoqin Yan, Yuchao Yang, Ru Huang:
Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption. 1-4 - Jiarui Bao, Shuyan Hu, Guangxi Hu, Laigui Hu, Ran Liu, Lirong Zheng:
A GaSb/In0.4Ga0.6As Heterojunction Z-Shaped Tunnel Field-Effect Transistor with High Performance. 1-4 - Bai Song Samuel Lee, Hang Liu, Xiaopeng Yu, Jer-Ming Chen, Kiat Seng Yeo:
An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS. 1-4 - Xubo Wang, Qing Wang, Jia Zhou:
Inverse RIE micro-loading in deep etching of silicon via array. 1-3 - Jieyang Li, Ting Yi, Zhiliang Hong:
A wide range and high resolution two-step TDC for millimeter-wave band ADPLL. 1-4 - Leilei Jin, Wenjie Fu, Yu Zheng, Hao Yan:
A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines. 1-4 - Yifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
EMI Noise Reduction and Output Ripple Cancellation for Full-Wave Type Soft-Switching Converter. 1-4 - Chongzhou Fang, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Training Adaptive Hardware for Reconfigurability: A Simplified Case Study. 1-4 - Li-Yi Xiao, Yuan-Gang Wang, Zu-Qiang Zhang, Jia-Qiang Li, Jie Li:
Radiation Hardened Design of Pipeline and Register File in Processor. 1-4 - Jincheng Zhang, Lihe Nie, Dong Wei, Tianxiang Wu, Shunli Ma, Junyan Ren:
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS. 1-4 - Yu-Lun Hsieh, Tai-Cheng Lee:
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling. 1-4 - Shogo Katayama, Jing Li, Yifei Sun, Minh Tri Tran, Yasunori Kobori, Anna Kuwana, Haruo Kobayashi:
Automatic Correction of Current Imbalance for Multi-Phase COT Ripple-Based Control DC-DC Converter. 1-4 - Leiou Wang, Donghui Wang:
An Automatically Selective Signal Combining Algorithm and System for Low SNR ECG Signals. 1-4 - Kun Peng, Yang Xu, Mingqian Sun:
Ultra-Low-Power CMOS Temperature Sensor for UHF RFID Systems. 1-4 - Songhao Guo, Li Ding, Jing Jin:
A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration. 1-4 - Shang Ma, Xuesi Wang, Yongjie Li, Kai Long, Bixin Zhu, Xin Lei:
A Low Complexity DDS Based On Optimized CORDIC Algorithm. 1-5 - Wei Jia Zhang, Jingshu Yu, Wai Tung Ng:
Smart Gate Driver ICs for GaN Power Transistors. 1-4 - Jingyi Wu, Hongyu Yu, Yang Jiang, Zeyu Wan, Siqi Lei, Wei-Chih Cheng, Guangnan Zhou, Robert Sokolovskij, Qing Wang, Guangrui Maggie Xia:
Oxygen-plasma-based digital etching for GaN/AlGaN high electron mobility transistors. 1-4 - Eddy Simoen, Alberto Vinicius Oliveira, Anabela Veloso, Adrian Vaisman Chasin, Romain Ritzenthaler, Hans Mertens, Naoto Horiguchi, Cor Claeys:
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. 1-4 - Qianlan Hu, Zhenfeng Zhang, Yanqing Wu:
High performance optoelectronics based on CVD Mos2. 1-3 - Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng:
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. 1-3 - Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren:
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. 1-4 - Hong-Xiang Li, Wen-Hui Li, Wei-Wei Chen, Peng-Jun Wang:
Design of the admittance detecting circuit for silicon waveguides using the capacitor-integration method. 1-4 - Zijie Zhou, Xiangliang Jin, Yang Wang, Peng Dong:
Design and Analysis of high robustness dual- direction SCR with heavily doping in N-Type Well. 1-4 - Yingying Liang, Xiaoming Liu, Jing Jin:
An Optimized Modeling Method for Transformer Design. 1-4 - Chang Yu, Xiaojing Lv, Yanhui Li, Tingting Mo:
A Sub-1dB NF Receiver for 1.5T Magnetic Resonance Imaging. 1-4 - Nan Qi, Nanjian Wu:
Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. 1-4 - Shixing Qiao, Hongliang Lv, Yuming Zhang, Yimen Zhang, Peng Ding:
An Improved InP HEMT Small Signal Model with RC Network. 1-4 - Linzhe Li, Liyi Xiao, Jie Li, He Liu, Zhigang Mao:
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. 1-4
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