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2020 – today
- 2024
[j42]Yongliang Chen
, Xiaole Cui, Xiaoxin Cui, Xing Zhang:
The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. Microelectron. J. 144: 106088 (2024)- [j41]Mingqi Yin, Xiaole Cui, Feng Wei, Hanqing Liu, Yuanyuan Jiang, Xiaoxin Cui:
A reconfigurable FPGA-based spiking neural network accelerator. Microelectron. J. 152: 106377 (2024) - [j40]Kefei Liu, Jingjie Shang, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Kanglin Xiao, Yi Zhong, Yuan Wang:
How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. IEEE Trans. Cogn. Dev. Syst. 16(3): 961-972 (2024) - [j39]Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang:
OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1899-1903 (2024) - [j38]Xin Qiao, Youming Yang, Chang Xue, Yandong He, Xiaoxin Cui, Song Jia, Yuan Wang:
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2539-2543 (2024) - [j37]Kanglin Xiao, Xin Qiao, Xiaoxin Cui, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang:
A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3263-3267 (2024) - [j36]Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui:
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells. ACM Trans. Design Autom. Electr. Syst. 29(1): 10:1-10:21 (2024) - [j35]Chen Wei, Xiaole Cui, Xiaoxin Cui:
Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays. IEEE Trans. Reliab. 73(1): 622-636 (2024) - [c53]Zilin Wang, Yi Zhong, Guang Chen, Shuo Feng, Youming Yang, Xiaoxin Cui, Yuan Wang:
A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. AICAS 2024: 154-158 - [c52]Hanqing Liu, Xiaole Cui, Sunrui Zhang, Mingqi Yin, Yuanyuan Jiang, Xiaoxin Cui:
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. ASAP 2024: 163-171 - [c51]Zhenhui Dai, Jiawei Wang, Yi Zhong, Kunyu Feng, Cheng Zhao, Yuanyuan Jiang, Peiyu Chen, Yuan Wang, Dunshan Yu, Xiaoxin Cui:
An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. ISCAS 2024: 1-5 - [c50]Yuanyuan Jiang, Li Lun, Jiawei Wang, Mingqi Yin, Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui:
SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. ISCAS 2024: 1-5 - [c49]Jiawei Wang, Li Lun, Zhenhui Dai, Yuanyuan Jiang, Xiaoxin Cui:
A 16.41 TOPS/W CNN Accelerator with Event-Based Layer Fusion for Real-Time Inference. ISCAS 2024: 1-5 - 2023
- [j34]Chenglong Zou, Xiaoxin Cui, Guang Chen, Yuanyuan Jiang, Yuan Wang:
Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. Adv. Intell. Syst. 5(12) (2023) - [j33]Kunyu Feng, Li Lun, Xiaofeng Wang, Xiaoxin Cui:
LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion. Remote. Sens. 15(22): 5309 (2023) - [j32]Sunrui Zhang, Xiaole Cui, Feng Wei, Xiaoxin Cui:
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. IEEE Trans. Computers 72(12): 3416-3430 (2023) - [j31]Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui:
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1380-1392 (2023) - [j30]Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang:
Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1590-1594 (2023) - [j29]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang:
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1816-1820 (2023) - [j28]Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang:
An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4241-4245 (2023) - [j27]Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui:
An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. IEEE Trans. Inf. Forensics Secur. 18: 1773-1788 (2023) - [c48]Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang:
Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. AICAS 2023: 1-5 - [c47]Zilin Wang, Yi Zhong, Youming Yang, Xiaoxin Cui, Yuan Wang:
An Efficient Spiking Neural Network Accelerator with Sparse Weight. BioCAS 2023: 1-5 - [c46]Zilin Wang, Yi Zhong, Xiaoxin Cui, Yisong Kuang, Yuan Wang:
A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. ISCAS 2023: 1-5 - 2022
- [j26]Yanjie Li, Xiaoxin Cui, Yihao Zhou, Ying Li:
A Comparative Study on the Performance and Security Evaluation of Spiking Neural Networks. IEEE Access 10: 117572-117581 (2022) - [j25]Chen Wei, Xiaole Cui, Xiaoxin Cui:
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec. IEEE Des. Test 39(5): 26-33 (2022) - [j24]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang:
A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectron. J. 126: 105506 (2022) - [j23]Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang:
Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. Microelectron. J. 129: 105612 (2022) - [j22]Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang:
A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2977-2981 (2022) - [j21]Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1631-1641 (2022) - [c45]Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang:
A Full-Neuron Memory Model Designed for Neuromorphic Systems. AICAS 2022: 138-141 - [c44]Xiuping Cui, Xiaochen Hao, Yun Liang, Guangyu Sun, Xiaoxin Cui, Yuan Wang, Ru Huang:
A Mapping Model of SNNs to Neuromorphic Hardware. AICAS 2022: 206-209 - [c43]Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang:
A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. AICAS 2022: 332-335 - [c42]Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui:
An obfuscation scheme of scan chain to protect the cryptographic chips. ATS 2022: 19-24 - [c41]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang:
A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. ICTA 2022: 182-183 - [c40]Qingyu Guo, Xiaoxin Cui, Jian Zhang, Aifei Zhang, Xinjie Guo, Yuan Wang:
A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. ISCAS 2022: 707-711 - [c39]Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang:
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. ISCAS 2022: 2551-2555 - [c38]Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang:
A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. ISCAS 2022: 2561-2565 - [c37]Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui:
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells. ISCAS 2022: 2571-2575 - [c36]Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang:
An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. ISCAS 2022: 3468-3472 - [i2]Ziming Wang, Shuang Lian, Yuhao Zhang, Xiaoxin Cui, Rui Yan, Huajin Tang:
Towards Lossless ANN-SNN Conversion under Ultra-Low Latency with Dual-Phase Optimization. CoRR abs/2205.07473 (2022) - 2021
- [j20]Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui:
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. IEEE Access 9: 54466-54477 (2021) - [j19]Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui:
28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance. IEICE Electron. Express 18(20): 20210309 (2021) - [j18]Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui:
Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption. J. Comput. Sci. Technol. 36(5): 1102-1117 (2021) - [j17]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang:
A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2655-2659 (2021) - [c35]Timothy Dunlap, Omid Aramoon, Gang Qu, Tian Wang, Xiaoxin Cui, Dunshan Yu:
A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates. AsianHOST 2021: 1-4 - [c34]Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui:
The logic obfuscation of LFSR with the crosstalk based polymorphic gate. AsianHOST 2021: 1-6 - [c33]Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang:
A fully asynchronous QDI mesh router based on 28nm standard cells. ASICON 2021: 1-4 - [c32]Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing. ACM Great Lakes Symposium on VLSI 2021: 83-88 - [c31]Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang:
An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor. IJCNN 2021: 1-8 - [c30]Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. ISCAS 2021: 1-5 - [c29]Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang:
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. ISCAS 2021: 1-5 - [c28]Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui:
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack. ITC 2021: 63-72 - [c27]Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui:
The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF. ITC-Asia 2021: 1-6 - [i1]Qingyu Guo, Yuan Wang, Xiaoxin Cui:
Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. CoRR abs/2106.00127 (2021) - 2020
- [j16]Xiaole Cui, Xiao Ma, Feng Wei, Xiaoxin Cui:
A synthesis method for logic circuits in RRAM arrays. Sci. China Inf. Sci. 63(10): 1-3 (2020) - [j15]Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui:
Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates. Circuits Syst. Signal Process. 39(6): 2822-2840 (2020) - [j14]Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang:
The synthesis method of logic circuits based on the iMemComp gates. Integr. 74: 115-126 (2020) - [c26]Li Qu, Xiaole Cui, Xiaoxin Cui:
A Testability Enhancement Method for the Memristor Ratioed Logic Circuits. ATS 2020: 1-6 - [c25]Chenglong Zou, Xiaoxin Cui, Jiexian Ge, Hanghang Ma, Xin'an Wang:
A Novel Conversion Method for Spiking Neural Network using Median Quantization. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c24]Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu:
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing. ASICON 2019: 1-4 - [c23]Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei:
BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead. ASICON 2019: 1-4 - [c22]Chenglong Zou, Xin'an Wang, Boxing Xu, Yisong Kuang, Xiaoxin Cui:
Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System. ASICON 2019: 1-4 - [c21]Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang:
An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. BioCAS 2019: 1-4 - [c20]Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang:
A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. ICICDT 2019: 1-4 - 2018
- [j13]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui:
Design of Low-Power High-Performance FinFET Standard Cells. Circuits Syst. Signal Process. 37(5): 1789-1806 (2018) - [j12]Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui:
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1922-1929 (2018) - [c19]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
Polymorphic gate based IC watermarking techniques. ASP-DAC 2018: 90-96 - [c18]Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang:
A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. BioCAS 2018: 1-4 - [c17]Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
A Novel Polymorphic Gate Based Circuit Fingerprinting Technique. ACM Great Lakes Symposium on VLSI 2018: 141-146 - 2017
- [j11]Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu:
Testing of 1TnR RRAM array with sneak path technique. Sci. China Inf. Sci. 60(2): 29402 (2017) - [j10]Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Improving DFA attacks on AES with unknown and random faults. Sci. China Inf. Sci. 60(4): 42401 (2017) - [j9]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ). IEEE Trans. Ind. Electron. 64(1): 727-738 (2017) - [j8]Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin:
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1601-1610 (2017) - [c16]Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu:
A practical cold boot attack on RSA private keys. AsianHOST 2017: 55-60 - [c15]Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Improving DFA on AES using all-fault ciphertexts. ASICON 2017: 283-286 - [c14]Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui:
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm. ASICON 2017: 742-745 - [c13]Kuimin Zhang, Xiaole Cui, Xiaoxin Cui:
A design of high performance full adder with memristors. ASICON 2017: 746-479 - [c12]Yixia Liu, Xiaoxin Cui, Jian Cao, Xing Zhang:
A hybrid fault model for differential fault attack on AES. ASICON 2017: 784-787 - [c11]Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui:
Design of router for spiking neural networks. ASICON 2017: 965-968 - [c10]Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui:
A Heuristic Algorithm for Automatic Generation of March Tests. ATS 2017: 266-271 - 2016
- [j7]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui:
Ultralow-power high-speed flip-flop based on multimode FinFETs. Sci. China Inf. Sci. 59(4): 042404:1-042404:11 (2016) - [j6]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu:
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology. IEICE Trans. Electron. 99-C(8): 974-983 (2016) - 2015
- [j5]Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu:
Key characterization factors of accurate power modeling for FinFET circuits. Sci. China Inf. Sci. 58(2): 1-13 (2015) - [j4]Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee:
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. IET Comput. Digit. Tech. 9(6): 300-310 (2015) - [c9]Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. ASICON 2015: 1-4 - [c8]Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui:
A countermeasure for power analysis to scalar multiplication of ECC hardware. ASICON 2015: 1-4 - [c7]Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui:
Employing the mixed FBB/RBB in the design of FinFET logic gates. ASICON 2015: 1-4 - 2014
- [j3]Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
Low power adiabatic logic based on FinFETs. Sci. China Inf. Sci. 57(2): 1-13 (2014) - [j2]Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs. Sci. China Inf. Sci. 57(4): 1-13 (2014) - [c6]Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu:
High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m). ISCAS 2014: 818-821 - 2013
- [j1]Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma:
Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices. IEICE Trans. Electron. 96-C(8): 1068-1075 (2013) - [c5]Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui:
AHardware implementation of DES with combined countermeasure against DPA. ASICON 2013: 1-4 - [c4]Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin:
New DfT architectures for 3D-SICs with a wireless test port. ASICON 2013: 1-4 - [c3]Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu:
A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs. ISCAS 2013: 129-132 - 2011
- [c2]Xun Jiang, Xiaoxin Cui, Dunshan Yu:
A JTAG-based configuration circuit applied in SerDes chip. ASICON 2011: 707-710
2000 – 2009
- 2006
- [c1]Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui:
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm. APCCAS 2006: 1753-1756
Coauthor Index
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