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ORCIDChung-Len Lee 0001
Person information
- affiliation: Peking University Shenzhen Graduate School, Key Lab of Integrated Microsystems, China
- affiliation: National Chiao Tung University, Department of Electronics Engineering, Institute of Electronics, Hsinchu, Taiwan
Other persons with the same name
- Chung-Len Lee (aka: Chung Len Lee, Chunglen Lee) — disambiguation page
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2010 – 2019
- 2016
[j25]Xiaole Cui, Zuolin Cheng, Chung-Len Lee, Xinnan Lin, Yiqun Wei, Xiaogang Chen, Zhitang Song:
A snake addressing scheme for phase change memory testing. Sci. China Inf. Sci. 59(10): 102401 (2016)- 2015
- [j24]Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee:
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure. IET Comput. Digit. Tech. 9(6): 300-310 (2015) - 2013
- [c44]Si Chen, Xiaole Cui, Chung Len Lee:
A novel test scheme for NAND flash memory based on built-in oscillator ring. ASICON 2013: 1-4 - [c43]Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin:
New DfT architectures for 3D-SICs with a wireless test port. ASICON 2013: 1-4 - [c42]Weijia Ma, Xiaole Cui, Chung Len Lee:
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. ASICON 2013: 1-4 - [c41]Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee:
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. ASICON 2013: 1-4 - [c40]Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee:
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. ASICON 2013: 1-4 - [c39]Xiangrong Zhang, Xiaole Cui, Bo Wang, Chung Len Lee:
A UWB mixer with a balanced wide band active balun using crossing centertaped inductor. ISCAS 2013: 1588-1591 - 2012
- [c38]Jin Zha, Xiaole Cui, Chung Len Lee:
Modeling and testing of interference faults in the nano NAND Flash memory. DATE 2012: 527-531
2000 – 2009
- 2009
- [j23]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 306-311 (2009) - 2008
- [c37]Weibo Hu, Chung Len Lee, Xin'an Wang:
Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer. DELTA 2008: 567-570 - 2007
- [j22]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. J. Electron. Test. 23(4): 341-355 (2007) - [j21]Katherine Shu-Min Li, Yao-Wen Chang
, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Multilevel Full-Chip Routing With Testability and Yield Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1625-1636 (2007) - [j20]Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 767-776 (2007) - 2006
- [j19]Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen:
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2513-2525 (2006) - [c36]Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. ASP-DAC 2006: 366-371 - [c35]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8 - 2005
- [c34]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Oscillation ring based interconnect test scheme for SOC. ASP-DAC 2005: 184-187 - [c33]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229 - [c32]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329 - [c31]Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen:
Finite State Machine Synthesis for At-Speed Oscillation Testability. Asian Test Symposium 2005: 360-365 - [c30]Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen:
Multilevel full-chip routing with testability and yield enhancement. SLIP 2005: 29-36 - 2004
- [c29]Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen:
A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. Asian Test Symposium 2004: 58-61 - [c28]Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Asian Test Symposium 2004: 145-150 - 2003
- [j18]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. J. Inf. Sci. Eng. 19(4): 637-651 (2003) - 2002
- [j17]Chih-Wen Lu, Chung-Len Lee, Chauchin Su, Jwu-E Chen:
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing. J. Electron. Test. 18(1): 89-97 (2002) - [j16]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Structural Fault Based Specification Reduction for Testing Analog Circuits. J. Electron. Test. 18(6): 571-581 (2002) - [j15]Chih-Wen Lu, Chung-Len Lee:
A low-power high-speed class-AB buffer amplifier for flat-panel-display application. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 163-168 (2002) - [c27]Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen:
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. Asian Test Symposium 2002: 170-175 - [c26]Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen:
An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. DATE 2002: 1119 - [c25]Chih-Wen Lu, Chung-Len Lee:
A Low Power High Speed Class-B Buffer Amplifier for Flat Panel Display Application. DELTA 2002: 172-176 - 2001
- [j14]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault Diagnosis for Linear Analog Circuits. J. Electron. Test. 17(6): 483-494 (2001) - [c24]Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee:
A computer aided engineering system for memory BIST. ASP-DAC 2001: 492-495 - 2000
- [j13]Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir:
Oscillation Ring Delay Test for High Performance Microprocessors. J. Electron. Test. 16(1-2): 147-155 (2000) - [j12]Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su:
A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. J. Inf. Sci. Eng. 16(5): 751-766 (2000) - [c23]Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
Fault diagnosis for linear analog circuits. Asian Test Symposium 2000: 25-30 - [c22]Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su:
A methodology for fault model development for hierarchical linear systems. Asian Test Symposium 2000: 90-95 - [c21]Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen:
Is IDDQ testing not applicable for deep submicron VLSI in year 2011? Asian Test Symposium 2000: 338-343 - [c20]Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee:
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. DATE 2000: 527-531
1990 – 1999
- 1999
- [j11]Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen:
A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. J. Inf. Sci. Eng. 15(6): 885-897 (1999) - [c19]Chauchin Su, Yue-Tsang Chen, Chung-Len Lee:
Analog Metrology and Stimulus Selection in a Noisy Environment. Asian Test Symposium 1999: 233-238 - [c18]Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen:
A DFT for semi-DC fault diagnosis for switched-capacitor circuits. ETW 1999: 58-63 - 1998
- [j10]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
A Two-Phase Fault Simulation Scheme for Sequential Circuits. J. Inf. Sci. Eng. 14(3): 669-686 (1998) - [c17]Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen:
Maximization of power dissipation under random excitation for burn-in testing. ITC 1998: 567-576 - [c16]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347 - 1997
- [j9]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1025-1033 (1997) - [c15]Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen:
Fault diagnosis of odd-even sorting networks. Asian Test Symposium 1997: 288- - [c14]Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
Functional test pattern generation for CMOS operational amplifier. VTS 1997: 267-273 - 1996
- [j8]Chung-Len Lee, Meng-Lieh Sheu:
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines. IEEE Trans. Computers 45(9): 1079-1083 (1996) - [c13]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15 - 1995
- [j7]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. 12(3): 14-23 (1995) - [j6]Beyin Chen, Chung-Len Lee:
Universal test set generation for CMOS circuits. J. Electron. Test. 6(3): 313-323 (1995) - [c12]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen:
Fanout fault analysis for digital logic circuits. Asian Test Symposium 1995: 33-39 - [c11]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen:
Identification of robust untestable path delay faults. Asian Test Symposium 1995: 229- - [c10]Meng-Lieh Sheu, Chung-Len Lee:
A programmable multiple-sequence generator for BIST applications. Asian Test Symposium 1995: 279-285 - [c9]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Factorization of Multi-Valued Logic Functions. ISMVL 1995: 164-169 - 1994
- [j5]Meng-Lieh Sheu, Chung-Len Lee:
Simplifying Sequential Circuit Test Generation. IEEE Des. Test Comput. 11(3): 28-38 (1994) - [j4]Beyin Chen, Chung-Len Lee:
A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 370-377 (1994) - [c8]Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee:
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. EDAC-ETC-EUROASIC 1994: 508-512 - [c7]Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin:
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. EDAC-ETC-EUROASIC 1994: 661 - [c6]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. ISMVL 1994: 44-51 - [c5]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Complete Test Set for Multiple-Valued Logic Networks. ISMVL 1994: 289-296 - 1992
- [j3]Chung Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang:
MT-SIM a mixed-level transition fault simulator based on parallel patterns. J. Electron. Test. 3(1): 67-78 (1992) - [c4]Ching Ping Wu, Chung Len Lee, Wen-Zen Shen:
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. EURO-DAC 1992: 446-449 - [c3]Hui Min Wang, Chung-Len Lee, Jwu E. Chen:
Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. ISMVL 1992: 181-188 - 1991
- [j2]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Checkpoints in irredundant two-level combinational circuits. J. Electron. Test. 2(4): 395-397 (1991) - [j1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault-collapsing analysis in sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1559-1568 (1991) - 1990
- [c2]Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu:
A Parallel Pattern Mixed-Level Fault Simulator. DAC 1990: 716-719 - [c1]Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen:
Single-fault fault collapsing analysis in sequential logic circuits. ITC 1990: 809-814
Coauthor Index
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