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2010 – 2019
- 2016
[j3]Kun-Lun Luo, Ming-Hsueh Wu, Chun-Lung Hsu, Chen-An Chen:
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM. J. Electron. Test. 32(2): 111-123 (2016)- 2013
- [c4]Chen-An Chen, Yee-Wen Chen, Chun-Lung Hsu, Ming-Hsueh Wu, Kun-Lun Luo, Bing-Chuan Bai
, Liang-Chia Cheng:
Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs. Asian Test Symposium 2013: 107-108 - [c3]Bing-Chuan Bai, Chun-Lung Hsu, Ming-Hsueh Wu, Chen-An Chen, Yee-Wen Chen, Kun-Lun Luo, Liang-Chia Cheng, James Chien-Mo Li:
Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM. Asian Test Symposium 2013: 123-127 - 2011
- [j2]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu:
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2184-2194 (2011)
2000 – 2009
- 2007
- [j1]Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 767-776 (2007) - 2006
- [c2]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8 - 2004
- [c1]Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang:
Fail Pattern Identification for Memory Built-In Self-Repair. Asian Test Symposium 2004: 366-371
Coauthor Index
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