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2020 – today
- 2021
[c8]Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng
, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. ETS 2021: 1-2- [c7]Hua-Ren Li, Hsing-Chung Liang:
GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer. ETS 2021: 1-2 - [c6]Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu:
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling. ITC 2021: 208-212 - 2020
- [c5]Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen:
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. DATE 2020: 1710-1711
2000 – 2009
- 2009
- [j6]Hsing-Chung Liang:
Improved Representatives for Judging Unrepairability and Deciding Economic Repair Solutions of Memories. J. Circuits Syst. Comput. 18(1): 81-95 (2009) - 2008
- [j5]Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang:
Testing Transition Delay Faults in Modified Booth Multipliers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1693-1697 (2008) - 2006
- [c4]Hsing-Chung Liang, Le-Quen Tzeng:
Improved Representatives for Unrepairability Judging and Economic Repair Solutions of Memories. MTDT 2006: 15 - 2005
- [j4]Hsing-Chung Liang, Wen-Chin Ho, Ming-Chieh Cheng:
Identify unrepairability to speed-up spare allocation for repairing memories. IEEE Trans. Reliab. 54(2): 358-365 (2005) - 2000
- [j3]Hsing-Chung Liang, Chung-Len Lee:
Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. J. Inf. Sci. Eng. 16(5): 687-702 (2000)
1990 – 1999
- 1999
- [c3]Hsing-Chung Liang, Chung-Len Lee:
An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. Asian Test Symposium 1999: 173-178 - 1998
- [c2]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. VTS 1998: 341-347 - 1997
- [j2]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying invalid states for sequential circuit test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1025-1033 (1997) - 1996
- [c1]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Invalid State Identification for Sequential Circuit Test Generation. Asian Test Symposium 1996: 10-15 - 1995
- [j1]Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
Identifying Untestable Faults in Sequential Circuits. IEEE Des. Test Comput. 12(3): 14-23 (1995)
Coauthor Index
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