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ORCIDShinichi Nishizawa
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2020 – today
- 2024
[j18]Thatree Mamee
, Zaiqi Lou, Katsuhiro Hata, Makoto Takamiya, Takayasu Sakurai, Shinichi Nishizawa, Wataru Saito:
Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN). IEEE Access 12: 96936-96945 (2024)- [j17]Ruilin Zhang, Haochen Zhang, Xingyu Wang, Ziyang Ye, Kunyang Liu, Shinichi Nishizawa, Kiichi Niitsu, Hirofumi Shinohara:
De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5187-5199 (2024) - 2023
- [j16]Zaiqi Lou, Thatree Mamee, Katsuhiro Hata, Makoto Takamiya, Shinichi Nishizawa, Wataru Saito:
IGBT Power Module Design for Suppressing Gate Voltage Spike at Digital Gate Control. IEEE Access 11: 6632-6640 (2023) - [j15]Shinichi Nishizawa, Toru Nakura:
Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 551-559 (2023) - [j14]Mingtao Zhang, Shinichi Nishizawa, Shinji Kimura:
Area Efficient Approximate 4-2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1714-1718 (2023) - [c23]Renrui Duan, Mingtao Zhang, Yi Guo, Shinichi Nishizawa, Shinji Kimura:
A Hardware-Efficient Approximate Multiplier Combining Inexact Same-weight N:2 Compressors and Remapping Logic with Error Recovery. SOCC 2023: 1-6 - [c22]Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Shinji Kimura:
Prime Factorization Based on Multiple Quantum Annealings on Partial Constraints with Analytical Variable Reduction. SOCC 2023: 1-6 - [c21]Zekun Wang, Shinichi Nishizawa, Shinji Kimura:
An 8-point Approximate DCT Design with Optimized Signed Digit Encoding. SOCC 2023: 1-6 - [c20]Mingtao Zhang, Ke Ma, Renrui Duan, Shinichi Nishizawa, Shinji Kimura:
Evaluation of Application-Independent Unbiased Approximate Multipliers on Quantized Convolutional Neural Networks. SOCC 2023: 1-6 - 2022
- [j13]Yuki Imai, Shinichi Nishizawa, Kazuhito Ito:
Reduction of LSI Maximum Power Consumption with Standard Cell Library of Stack Structured Cells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 487-496 (2022) - [j12]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5568-5581 (2022) - [c19]Shinichi Nishizawa, Toru Nakura:
Density Aware Cell Library Design for Design-Technology Co-Optimization. ISQED 2022: 1 - 2021
- [j11]Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021) - 2020
- [j10]Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi:
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. IPSJ Trans. Syst. LSI Des. Methodol. 13: 56-64 (2020) - [c18]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD 2020: 157:1-157:8
2010 – 2019
- 2019
- [j9]Kota Chubachi, Shinichi Nishizawa, Kazuhito Ito:
Analog circuit design methodology utilizing a structure of thin BOX FDSOI. IEICE Electron. Express 16(5): 20181136 (2019) - [c17]Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa:
Switching of 3300V Scaled IGBT by 5V Gate Drive. ASICON 2019: 1-3 - [c16]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC 2019: 120 - [c15]Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi:
Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. IOLTS 2019: 305-309 - [c14]A. K. M. Mahfuzul Islam, Shinichi Nishizawa, Yusuke Matsui, Yoshinobu Ichida:
Drive-Strength Selection for Synthesis of Leakage-Dominant Circuits. ISQED 2019: 298-303 - 2018
- [j8]Shinichi Nishizawa, Hidetoshi Onodera:
Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2222-2230 (2018) - [j7]Kazuhito Ito, Yuto Ishihara, Shinichi Nishizawa:
Minimization of Vote Operations for Soft Error Detection in DMR Design with Error Correction by Operation Re-Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2271-2279 (2018) - [j6]Kazunori Hasegawa, Kousuke Tsuzaki, Shinichi Nishizawa:
DC-bias-voltage dependence of degradation of aluminum electrolytic capacitors. Microelectron. Reliab. 83: 115-118 (2018) - [j5]Kazunori Hasegawa, Shinichi Nishizawa, Ichiro Omura:
ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier. Microelectron. Reliab. 88-90: 433-437 (2018) - [c13]Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai:
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC 2018: 26-29 - [c12]Shinichi Nishizawa, Hidetoshi Onodera:
Process variation aware D-Flip-Flop design using regression analysis. ISQED 2018: 88-93 - [c11]Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai:
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits 2018: 105-106 - 2017
- [c10]Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai:
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON 2017: 1137-1140 - [c9]Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61 - 2016
- [j4]Kazunori Hasegawa, Kentaro Kozuma, Kousuke Tsuzaki, Ichiro Omura, Shinichi Nishizawa:
Temperature rise measurement for power-loss comparison of an aluminum electrolytic capacitor between sinusoidal and square-wave current injections. Microelectron. Reliab. 64: 98-100 (2016) - [j3]Kazunori Hasegawa, Ichiro Omura, Shinichi Nishizawa:
Design and Analysis of a New Evaluation Circuit for Capacitors Used in a High-Power Three-Phase Inverter. IEEE Trans. Ind. Electron. 63(5): 2679-2687 (2016) - 2015
- [j2]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. IPSJ Trans. Syst. LSI Des. Methodol. 8: 131-135 (2015) - [c8]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
An impact of process variation on supply voltage dependence of logic path delay variation. VLSI-DAT 2015: 1-4 - 2014
- [c7]Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. SoCC 2014: 17-22 - [c6]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. SoCC 2014: 42-47 - 2013
- [j1]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2499-2507 (2013) - [c5]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
Analysis and comparison of XOR cell structures for low voltage circuit design. ISQED 2013: 703-708 - 2012
- [c4]Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A flexible structure of standard cell and its optimization method for near-threshold voltage operation. ICCD 2012: 235-240 - [c3]Masahiro Kondo, Shinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera:
A Standard Cell Optimization Method for Near-Threshold Voltage Operations. PATMOS 2012: 32-41 - 2011
- [c2]Kyosuke Ito, Takashi Matsumoto, Shinichi Nishizawa, Hiroki Sunagawa, Kazutoshi Kobayashi, Hidetoshi Onodera:
Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. ISQED 2011: 22-27
2000 – 2009
- 2009
- [c1]Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui:
An Efficient Hardware Accelerator for Power Grid Simulation. ISCAS 2009: 2994-2997
Coauthor Index
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