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ORCID30th SoCC 2017: Munich, Germany
- Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar:
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. IEEE 2017, ISBN 978-1-5386-4034-0 - Thomas Leyrer:
T1A: Time sensitive networks for industry 4.0. 1 - Helen Li:
Technical program overview. 1 - Michael Pronath:
Low power circuit optimization for IoT. 1-2 - Ching-Yuan Yang:
W2A: Analog-to-digital converters and low-noise amplifiers. 1 - Jörg Henkel:
The triangle of power density, circuit degradation and reliability. 1-2 - Mostafa Khamis:
F1A: Networks on chip. 1 - Gerd Teepe:
Wednesday keynote I: FDSOI and FINFET for SoC developments. 1-2 - Jörg Henkel:
The triangle of power density, circuit degradation and reliability. 1 - Herbert Preuthen, Jurgen Dirks:
FDSOI design experience and recommendations. 1-2 - Ron Martino:
Wednesday keynote II: Advanced technology for automotive cockpits, industrial human-machine-interface and IoT systems - Optimization of technology - Architecture - Design. 1-3 - Subhadeep Ghosh, Scott Martin, Shane Stelmach:
Reliability for IoT and automotive markets. 1-3 - Thomas Leyrer:
Time sensitive networks for industry 4.0. 1-2 - Davide Bertozzi, Sébastien Rumley:
Propelling breakthrough embedded microprocessors by means of integrated photonics. 1-3 - Tolga Soyata:
W3A: Design of reconfigurable and multiprocessor systems. 1 - Harsh Rawat, K. Bharath, Alexander Fell
:
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. 1-6 - Amlan Ganguly:
W1B: Application specific designs. 1 - Jürgen Becker:
Opening remarks. 1 - Bing Li:
W3B: Special session: Secure multi-processors systems-on-chip for critical applications. 1 - Eduardo Wächter:
F2A: Low power design. 1 - Robert Wille, Bing Li:
Design automation for Labs-on-Chip: A new "playground" for SoC designers. 1-2 - Mircea Stan:
Panel discussion: Autonomy, technology, safety - Where will automotive electronics go in the next decade? 1 - Andrew Marshall, Nishtha Sharma:
The importance of benchmarking for charge-based and beyond CMOS devices. 1-2 - M. B. Srinivas:
T2A: Analog and RF circuits. 1 - Vivek Nautiyal:
W2B: Design methodologies for SoCs. 1 - Norbert Wehn:
The memory challenge in computing systems: A survey. 1-2 - Albert Frisch:
IBM Q - Introduction into quantum computing with live demo. 1-2 - Johanna Sepúlveda:
T1B: Special session: Data analytics driven design for yield, manufacturability and reliability: Where machine learning meets design automation. 1 - Bei Yu:
F1B: Algorithms, models and simulation for systems. 1 - Norbert Wehn:
The memory challenge in computing systems: A survey. 1 - Josef Hausner:
The path to global connectivity - Wireless communication enters the next generation. 1-2 - Hai Helen Li:
W1A: Memories. 1 - Chung-Ta King:
F2B: On-chip fabrics. 1 - Jürgen Becker:
Opening remarks. 1 - Thorsten Lorenzen:
T2B: Machine learning and parallel architectures. 1 - Renyuan Zhang, Mineo Kaneko:
A random access analog memory with master-slave structure for implementing hexadecimal logic. 7-11 - Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade:
An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors. 12-17 - Kyeongryeol Bong, Kyuho Jason Lee, Hoi-Jun Yoo:
A 590MDE/s semi-global matching processor with lossless data compression. 18-22 - Ahmed S. Alshammari, Mohamed I. Sobhy, Peter Lee:
Secure digital communication based on Lorenz stream cipher. 23-28 - Daniel Florez, Johanna Sepúlveda:
BlooXY: On a non-invasive blood monitor for the IoT context. 29-34 - Youngtae Yang, Jaehoon Jun, Suhwan Kim:
A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC. 35-39 - Javed S. Gaggatur, Gaurab Banerjee:
A 13.5 bit 1.6 mW 3rd order CT ΣΔ ADC for integrated capacitance sensor interface. 40-44 - Mahesh Kumar Adimulam, Krishna Kumar Movva, M. B. Srinivas:
A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications. 45-50 - Zhengnan Yan, Mohamed Atef, Guoxing Wang, Yong Lian:
Low-noise high input impedance 8-channels chopper-stabilized EEG acquisition system. 51-55 - Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. 56-61 - Muhammad Obaidullah, Gul N. Khan:
Hybrid multi-swarm optimization based NoC synthesis. 62-67 - Jose Eduardo Chiarelli Bueno Filho, Jiang Chau Wang:
Multifractal on-chip traffic generation under TLM. 68-73 - Praveen Kumar, Alexander Fell, Sachin Mathur:
Automated, inter-macro channel space adjustment and optimization for faster design closure. 74-79 - Takashi Imagawa, Koki Honda, Hiroyuki Ochi:
Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. 80-85 - Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari:
Robust throughput boosting for low latency dynamic partial reconfiguration. 86-90 - Takumi Fujimori, Minoru Watanabe:
Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array. 91-95 - Marco Pagani, Alessio Balsini, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo:
A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration. 96-101 - Ilia Polian, Francesco Regazzoni, Johanna Sepúlveda:
Introduction to hardware-oriented security for MPSoCs. 102-107 - El Mehdi Benhani, Cédric Marchand, Alain Aubert, Lilian Bossuet:
On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC. 108-113 - Nisha Jacob, Jakob Wittmann, Johann Heyszl, Robert Hesselbarth, Florian Wilde, Michael Pehl, Georg Sigl, Kai Fischer:
Securing FPGA SoC configurations independent of their manufacturers. 114-119 - Johanna Sepúlveda, Andreas Zankl, Oliver Mischke:
Cache attacks and countermeasures for NTRUEncrypt on MPSoCs: Post-quantum resistance for the IoT. 120-125 - Ronny García-Ramírez, Alfonso Chacon-Rodriguez, Renato Rimolo-Donadio:
A 0.13 CMOS integrated circuit for electrical impedance spectroscopy from 1 kHz to 10 GHz. 126-131 - Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, Amlan Ganguly:
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects. 132-137 - Dongjoo Shin, Youchang Kim, Hoi-Jun Yoo:
A 1.41mW on-chip/off-chip hybrid transposition table for low-power robust deep tree search in artificial intelligence SoCs. 138-142 - Jeong H. Choi, Kwang Sub Yoon:
A CMOS third order ΔΣ modulator with inverter-based integrators. 143-148 - Mostafa Said, Hossam Hassan, HyungWon Kim, Mostafa Khamis:
A novel power reduction technique using wire multiplexing. 149-152 - Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker:
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. 153-158 - Mihir N. Mody, Manu Mathew, Shyam Jagannathan, Arthur Redfern, Jason Jones, Thorsten Lorenzen:
CNN inference: VLSI architecture for convolution layer for 1.2 TOPS. 158-162 - Haipeng Lin, Amir Zjajo, Rene van Leuken:
Digital spiking neuron cells for real-time reconfigurable learning networks. 163-168 - Yun Long Lan, V. Muthukumar:
Efficient virtual channel allocator for NoC router micro-architecture. 169-174 - Ahmed Y. Ginawi, Robert Gauthier, Tian Xia:
Investigation of diode triggered silicon control rectifier turn-on time during ESD events. 175-178 - Nishtha Sharma, Jonathan Bird, Peter Dowben, Andrew Marshall:
Magneto-electric magnetic tunnel junction based analog circuit options. 179-183 - Tung Thanh Le, Rui Ning, Dan Zhao, Hongyi Wu, Magdy A. Bayoumi:
Optimizing the heterogeneous network on-chip design in manycore architectures. 184-189 - Thawra Kadeed, Eberle A. Rambo, Rolf Ernst:
Power and area evaluation of a fault-tolerant network-on-chip. 190-195 - Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi:
Selectable grained reconfigurable architecture (SGRA) and its design automation. 196-201 - Sri Navaneeth Easwaran, Samir Camdzic, Robert Weigel:
Thermal simulation aided 98mJ integrated high side and low side drivers design for safety SOCs. 202-205 - Todd Hiers, Chunhua Hu, Brian Karguth, Chuck Fuoco:
Virtual white board: Leveraging investments in interface based design and executable specification. 206-210 - Ching-Yuan Yang, Jen-Yan Huang, Jun-Hong Weng:
Realization of buck converter with adaptive variable-frequency control. 211-214 - Mohamadhadi Habibzadeh, Moeen Hassanalieragh, Tolga Soyata, Gaurav Sharma:
Supercapacitor-based embedded hybrid solar/wind harvesting system architectures. 215-220 - Lucie Broyde, Kent W. Nixon, Xiang Chen, Hai Li, Yiran Chen:
MobiCore: An adaptive hybrid approach for power-efficient CPU management on Android devices. 221-226 - Cheng Zhuo, Bei Yu, Di Gao:
Accelerating chip design with machine learning: From pre-silicon to post-silicon. 227-232 - Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young:
Lithography hotspot detection: From shallow to deep learning. 233-238 - Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi:
Generative adversarial network based scalable on-chip noise sensor placement. 239-242 - Baris Yigit, Grace Li Zhang, Bing Li, Yiyu Shi, Ulf Schlichtmann:
Application of machine learning methods in post-silicon yield improvement. 243-248 - Hyunjong Kim, Yujin Park, Han Yang, Suhwan Kim:
A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique. 249-252 - Jan Plíva, Mahdi M. Khafaji, László Szilágyi, Ronny Henker, Frank Ellinger:
Opto-electrical analog front-end with rapid power-on and 0.82 pJ/bit for 28 Gb/s in 14 nm FinFET CMOS. 253-257 - Wei-Lun Ou, Yu-Kai Tsai, Po-Yen Tseng, Liang-Hung Lu:
A 2.4-GHz dual-mode resizing power amplifier with a constant conductance output matching. 258-261 - Atef H. Bondok, Awny M. El-Mohandes, Ahmed Shalaby, Mohammed Sharaf Sayed:
A low complexity UWB PHY baseband transceiver for IEEE 802.15.6 WBAN. 262-267 - Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson:
FPGA-based CNN inference accelerator synthesized from multi-threaded C software. 268-273 - Lizheng Liu, Yi Jin, Yi Liu, Ning Ma, Zhuo Zou, Lirong Zheng:
Designing bio-inspired autonomous error-tolerant massively parallel computing architectures. 274-279 - Hantao Huang, Leibin Ni, Hao Yu:
LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network. 280-285 - Akshay Srivatsa, Sven Rheindt, Thomas Wild, Andreas Herkersdorf:
Region based cache coherence for tiled MPSoCs. 286-291 - Sebastian Tobuschat, Rolf Ernst:
Providing throughput guarantees in mixed-criticality networks-on-chip. 292-297 - Sayed Taha Muhammad, Ali A. El-Moursy, Magdy A. El-Moursy, Hesham F. A. Hamed:
System-level simulator for process variation influenced synchronous and asynchronous NoCs. 298-303 - Zicong Wang, Xiaowen Chen, Chen Li, Yang Guo:
Fairness-oriented switch allocation for networks-on-chip. 304-309 - Mingmin Bai, Dan Zhao, Magdy A. Bayoumi:
Router-level performance driven dynamic management in hierarchical networks-on-chip. 310-315 - Hao-Lun Wei, Chung-Ta King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu:
Application specific component-service-aware trace generation on Android-QEMU. 316-321 - Nana Sutisna, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi:
A unified HW/SW system-level simulation framework for next generation wireless system. 322-327 - Mousumi Bhanja, Baidyanath Ray:
A graph based synthesis procedure for linear analog function. 328-333 - Jeremy Schlachter, Mike Fagan, Krishna V. Palem, Christian C. Enz:
A study on the energy-precision tradeoffs on commercially available processors and SoCs with an EPI based energy model. 334-339 - Sai Praveen Kadiyala, Vikram Kumar Pudi, Siew-Kei Lam:
Approximate compressed sensing for hardware-efficient image compression. 340-345 - Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen:
Content-aware line-based power modeling methodology for image signal processor. 346-350 - Alberto Nannarelli:
A multi-format floating-point multiplier for power-efficient operations. 351-356 - Md Shahriar Shamim, M. Meraj Ahmed, Naseef Mansoor, Amlan Ganguly:
Energy-efficient wireless interconnection framework for multichip systems with in-package memory stacks. 357-362 - Vinicius Fochi, Luciano L. Caimi, Marcelo Ruaro, Eduardo Wächter, Fernando Gehm Moraes:
System management recovery protocol for MPSoCs. 367-374 - Nicoleta Cucu Laurenciu, Sorin Dan Cotofana:
Haar-based interconnect coding for energy effective medium/long range data transport. 375-380 - György Rácz, Péter Arató:
A decomposition-based system level synthesis method for heterogeneous multiprocessor architectures. 381-386
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