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ORCIDVivek Nautiyal
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2020 – today
- 2024
[c10]Vivek Nautiyal:
Efficient Repair Configuration Algorithm, for Improving Yield of Semiconductor Memories. CCWC 2024: 22-27- 2021
- [c9]Vivek Nautiyal, Gaurav Singla, Bikas Maiti, Martin Kinkade:
Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies. ISCAS 2021: 1-4
2010 – 2019
- 2018
- [c8]Vivek Nautiyal, Gaurav Singla, Sagar Dwivedi, Satinderjit Singh, Ingming Chang, Jitendra Dasani, Fakhruddin Ali Bohra:
Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies. ISCAS 2018: 1-5 - [c7]Vivek Nautiyal, Nishant Nukala, Fakhruddin Ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade:
Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs. ISQED 2018: 274-279 - 2017
- [c6]Vivek Nautiyal, Gaurav Singla, Satinderjit Singh, Fakhruddin Ali Bohra, Jitendra Dasani, Lalit Gupta, Sagar Dwivedi:
Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET. ISLPED 2017: 1-6 - [c5]Anindhya Sankhla, Vinanti Kalangutkar, Himadri B. G. S. Bhuyan, Tanwi Mallick, Vivek Nautiyal
, Partha Pratim Das, Arun Kumar Majumdar:
Automated Translation of Human Postures from Kinect Data to Labanotation. NCVPRIPG 2017: 494-505 - [c4]Vivek Nautiyal:
W2B: Design methodologies for SoCs. SoCC 2017: 1 - [c3]Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Sagar Dwivedi, Martin Kinkade:
An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors. SoCC 2017: 12-17 - [c2]Vivek Nautiyal, Gaurav Singla, Lalit Gupta, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade:
Robust, self-timed power-on reset circuit for low-voltage applications. VLSI-SoC 2017: 1-6 - [c1]Vivek Nautiyal, Lalit Gupta, Gaurav Singla, Jitendra Dasani, Sagar Dwivedi, Martin Kinkade:
Self-timed Power-on Reset Circuit for Pseudo Dual/Two Port SRAM Used in Low-Voltage IoT Applications. VLSI-SoC (Selected Papers) 2017: 92-111
Coauthor Index
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