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Roberto Yusi Omaki
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2010 – 2019
- 2017
- [c6]Ryosuke Koike, Takashi Imagawa, Roberto Yusi Omaki, Hiroyuki Ochi:
Selectable grained reconfigurable architecture (SGRA) and its design automation. SoCC 2017: 196-201 - 2014
- [c5]Hiroyuki Okuhata, Rintaro Imai, Masanao Ise, Roberto Yusi Omaki, Hajime Nakamura, Shinsuke Hara, Isao Shirakawa:
Implementation of dynamic-range enhancement and super-resolution algorithms for medical image processing. ICCE 2014: 181-184 - 2013
- [c4]Hiroyuki Okuhata, Masanao Ise, Roberto Yusi Omaki, Isao Shirakawa:
Implementation of super-resolution scaler for Full HD and 4K video. ICCE-Berlin 2013: 1-5
2000 – 2009
- 2006
- [j2]Zhaohui Guo, Yuuki Nishikawa, Roberto Yusi Omaki, Takao Onoye, Isao Shirakawa:
A low-complexity FEC assignment scheme for motion JPEG2000 over wireless network. IEEE Trans. Consumer Electron. 52(1): 81-86 (2006) - 2002
- [j1]Roberto Yusi Omaki, Gen Fujita, Takao Onoye, Isao Shirakawa:
An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 703-713 (2002) - 2001
- [c3]Roberto Yusi Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa:
Realtime wavelet video coder based on reduced memory accessing. ASP-DAC 2001: 15-16 - 2000
- [c2]Roberto Yusi Omaki, Yu Dong, M. Horgan Miki, Makoto Furuie, Shohei Yamada, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa:
VLSI implementation of a realtime wavelet video coder. CICC 2000: 543-546 - [c1]Yu Dong, Roberto Yusi Omaki, Takao Onoye, Isao Shirakawa:
VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder. ICIP 2000: 126-129
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