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2020 – today
- 2024
[c132]Minoru Watanabe:
Analysis of Clock Tree Buffer Degradation Caused by Radiation. ARC 2024: 120-133- [c131]Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe:
Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. ASAP 2024: 239-240 - [c130]Sae Goto, Minoru Watanabe, Akifumi Ogiwara, Nobuya Watanabe:
Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory. ICCE 2024: 1-2 - [c129]Akifumi Ogiwara, Minoru Watanabe:
Holographic memory formed by different laser wavelengths in laser combiner system for optically reconfigurable gate array. ICCE 2024: 1-4 - [c128]Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe:
Remote monitoring system for optically reconfigurable gate arrays in radiation environments. ICCE 2024: 1-2 - [c127]Atsushi Takata, Minoru Watanabe, Nobuya Watanabe:
Wafer-scale VLSI realization using programmable architecture. ICCE 2024: 1-2 - [c126]Nobuya Watanabe, Ryoya Ishitani, Minoru Watanabe:
Application design system for high-speed dynamically reconfigurable gate arrays. ICCE 2024: 1-6 - [c125]Minoru Watanabe, Makoto Inami Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shigeo Matsuyama, Misako Miwa:
Fast-neutron soft-error tolerance experimentation with a radiation-hardened optically reconfigurable gate array. ICCE 2024: 1-2 - [c124]Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe:
Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI. SOCC 2024: 1-6 - 2023
- [c123]Daisuke Bamba, Minoru Watanabe, Nobuya Watanabe:
Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor. ICCE 2023: 1-2 - [c122]Takato Tanizawa, Minoru Watanabe:
Radiation-hardened stabilized power supply unit based on bipolar transistors. ICM 2023: 313-316 - [c121]Minoru Watanabe:
Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock. ISCAS 2023: 1-5 - [c120]Kakeru Ando, Minoru Watanabe, Nobuya Watanabe:
Multi-context-scrubbing operation for a 1-bit counter circuit. NEWCAS 2023: 1-4 - [c119]Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe:
An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit. SOCC 2023: 1-5 - 2022
- [c118]Sae Goto, Minoru Watanabe, Nobuya Watanabe:
Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration. APCCAS 2022: 241-245 - [c117]Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya:
Convolutional neural network implementations using Vitis AI. CCWC 2022: 365-371 - [c116]Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe:
Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI. ICECS 2022 2022: 1-4 - 2021
- [c115]Hirotoshi Ito, Minoru Watanabe:
Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation. FPT 2021: 1-4 - [c114]Kurea Murakami, Minoru Watanabe:
Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs. ISCAS 2021: 1-5
2010 – 2019
- 2019
- [c113]Masaki Watanabe, Minoru Watanabe:
Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation. APCCAS 2019: 177-181 - [c112]Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano:
FPGA implementation of a robot control algorithm. ETFA 2019: 1571-1574 - [c111]Hirotoshi Ito, Minoru Watanabe:
Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array. SoCC 2019: 306-311 - 2018
- [j5]Minoru Watanabe:
Foreword. IEICE Trans. Inf. Syst. 101-D(2): 277 (2018) - [c110]Takumi Fujimori, Minoru Watanabe:
A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory. AHS 2018: 218-224 - [c109]Takumi Fujimori, Minoru Watanabe:
High total-ionizing-dose tolerance field programmable gate array. ISCAS 2018: 1-4 - [p1]Masato Motomura, Masanori Hariyama, Minoru Watanabe:
Advanced Devices and Architectures. Principles and Structures of FPGAs 2018: 207-231 - 2017
- [c108]Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara:
500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA. AHS 2017: 167-171 - [c107]Hiroki Shinba, Minoru Watanabe:
Optically reconfigurable gate array platform for mono-instruction set computer architecture. CCWC 2017: 1-4 - [c106]Takumi Fujimori, Minoru Watanabe:
Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays. DASC/PiCom/DataCom/CyberSciTech 2017: 620-625 - [c105]Takumi Fujimori, Minoru Watanabe:
Multi-context scrubbing method. MWSCAS 2017: 1548-1551 - [c104]Takumi Fujimori, Minoru Watanabe:
Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array. SoCC 2017: 91-95 - 2016
- [c103]Shinya Furukawa, Ili Shairah Abdul Halim
, Minoru Watanabe, Fuminori Kobayashi:
Direct optical communication on an optically reconfigurable gate array. FGCT 2016: 17-20 - [c102]Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara:
A 200 Mrad Radiation Tolerance of a Polymer-Dispersed Liquid Crystal Holographic Memory. HPCC/SmartCity/DSS 2016: 1534-1535 - [c101]Takumi Fujimori, Minoru Watanabe:
Full FPGA game machine. ICCE 2016: 431-432 - [c100]Bharat Ramanathan, Minoru Watanabe:
Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays. ICCSE 2016: 454-457 - [c99]Tomoya Akabe, Minoru Watanabe:
Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays. VLSID 2016: 603-604 - 2015
- [c98]Minoru Watanabe, Takumi Fujimori:
Holographic scrubbing technique for a programmable gate array. AHS 2015: 1-5 - [c97]Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara:
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. ARC 2015: 393-400 - [c96]Takumi Fujimori, Minoru Watanabe:
Parallel-Operation-Oriented Optically Reconfigurable Gate Array. ARCS 2015: 3-14 - [c95]Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe:
FPGA Trax Solver based on a neural network design. FPT 2015: 260-263 - [c94]Minoru Watanabe:
Sustainable advantage of a parallel configuration in an optical FPGA. SII 2015: 807-810 - 2014
- [c93]Takashi Yoza, Minoru Watanabe:
Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation. ARC 2014: 156-166 - [c92]Retsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe:
Optically reconfigurable gate array with an angle-multiplexed holographic memory. ACM Great Lakes Symposium on VLSI 2014: 341-346 - [c91]Takumi Fujimori, Minoru Watanabe:
Radiation Tolerance of Color Configuration on an Optically Reconfigurable Gate Array. IPDPS Workshops 2014: 205-210 - [c90]Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito:
Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture. ISCAS 2014: 1528-1531 - 2013
- [c89]Yuichiro Yamaji, Minoru Watanabe:
Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method. AHS 2013: 172-177 - [c88]Yuya Shirahashi, Minoru Watanabe:
Dependability-Increasing Method of Processors under a Space Radiation Environment. ARC 2013: 218 - [c87]Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito:
Image recognition operation on a dynamically reconfigurable vison architecture. FPL 2013: 1-4 - [c86]Takumi Fujimori, Minoru Watanabe:
Color configuration method for an optically reconfigurable gate array. FPT 2013: 406-409 - [c85]Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. FPT 2013: 494-497 - [c84]Takayuki Kubota, Minoru Watanabe:
0.18 μm CMOS process photodiode memory. ISCAS 2013: 1464-1467 - [c83]Akira Tanigawa, Minoru Watanabe:
Dependability-increasing technique for a multi-context optically reconfigurable gate array. ISCAS 2013: 1568-1571 - [c82]Hiroyuki Ito, Minoru Watanabe:
Fourier transformation on an optically reconfigurable gate array. MWSCAS 2013: 193-196 - 2012
- [j4]Takahiro Watanabe, Minoru Watanabe:
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. SIGARCH Comput. Archit. News 40(5): 82-86 (2012) - [c81]Takashi Yoza, Minoru Watanabe:
A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. AHS 2012: 92-98 - [c80]Takahiro Watanabe, Minoru Watanabe:
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. ARC 2012: 163-173 - [c79]Takashi Yoza, Minoru Watanabe:
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. FPL 2012: 361-366 - [c78]Takahiro Watanabe, Minoru Watanabe:
High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. IPDPS Workshops 2012: 256-260 - [c77]Takahiro Watanabe, Minoru Watanabe:
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. ISVLSI 2012: 308-313 - [c76]Takahiro Watanabe, Minoru Watanabe:
Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. MWSCAS 2012: 117-120 - [c75]Hiroyuki Ito, Minoru Watanabe:
A Uniform Partitioning Method for Mono-Instruction Set Computer (MISC). NBiS 2012: 832-837 - [c74]Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito:
Gray-level image recognition on a dynamically reconfigurable vision architecture. SoCC 2012: 61-65 - 2011
- [j3]Shinya Kubota, Minoru Watanabe:
A MEMS writer system embedded for a programmable optically reconfigurable gate array. SIGARCH Comput. Archit. News 39(4): 94-97 (2011) - [j2]Mao Nakajima, Minoru Watanabe:
Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control. ACM Trans. Reconfigurable Technol. Syst. 4(2): 15:1-15:21 (2011) - [c73]Takayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi:
Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. AHS 2011: 44-49 - [c72]Hironobu Morita, Minoru Watanabe:
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. ARC 2011: 242-252 - [c71]Takahiro Watanabe, Minoru Watanabe:
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. FPL 2011: 34-37 - [c70]Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe:
An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT 2011: 1-4 - [c69]Yuki Torigai, Minoru Watanabe:
Triple module redundancy scheme on an optically reconfigure gate array. ISOCC 2011: 250-253 - [c68]Yuichiro Yamaji, Minoru Watanabe:
A 144-configuration context MEMS optically reconfigurable gate array. SoCC 2011: 237-241 - 2010
- [c67]Hironobu Morita, Minoru Watanabe:
Binary MEMS Optically Reconfigurable Gate Array. ACIS-ICIS 2010: 63-68 - [c66]Daisaku Seto, Minoru Watanabe:
Recovery method for a turn-off failure mode of a laser array on an ORGA. AHS 2010: 235-240 - [c65]Yuji Aoyama, Minoru Watanabe:
Acceleration method of optical reconfigurations using analog configuration contexts. AHS 2010: 304-308 - [c64]Daisaku Seto, Minoru Watanabe:
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. ARC 2010: 134-144 - [c63]Daisaku Seto, Minoru Watanabe:
Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays. DFT 2010: 411-419 - [c62]Daisaku Seto, Minoru Watanabe:
Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array. ERSA 2010: 232-237 - [c61]Maki Yasuda, Minoru Watanabe:
Dynamically Reconfigurable Vision-Chip Architecture. FPL 2010: 508-512 - [c60]Yuichiro Yamaji, Minoru Watanabe:
A 64-context MEMS optically reconfigurable gate array. FPT 2010: 499-502 - [c59]Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe:
Othello Solver based on a soft-core MIMD processor array. FPT 2010: 511-514 - [c58]Mao Nakajima, Minoru Watanabe:
A 100-context optically reconfigurable gate array. ISCAS 2010: 2884-2887 - [c57]Yuji Aoyama, Minoru Watanabe:
Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array. SoCC 2010: 243-247
2000 – 2009
- 2009
- [c56]Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara:
Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory. AHS 2009: 106-111 - [c55]Mao Nakajima, Minoru Watanabe:
A Sixteen-Context Dynamic Optically Reconfigurable Gate Array. AHS 2009: 120-125 - [c54]Mao Nakajima, Minoru Watanabe:
Fast Optical Reconfiguration of a Nine-Context DORGA. ARC 2009: 123-132 - [c53]Mao Nakajima, Minoru Watanabe:
A 16-context Optically Reconfigurable Gate Array. ASAP 2009: 227-230 - [c52]Daisaku Seto, Minoru Watanabe:
An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. ASP-DAC 2009: 117-118 - [c51]Shinya Kubota, Minoru Watanabe:
A Multi-Context Programmable Optically Reconfigurable Gate Array. ERSA 2009: 305-306 - [c50]Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara:
Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory. ERSA 2009: 307-308 - [c49]Hironobu Morita, Minoru Watanabe:
Alignment compensation method for an optically reconfigurable gate array. ERSA 2009: 332-333 - [c48]Hironobu Morita, Minoru Watanabe:
Mems optically reconfigurable gate array. FPL 2009: 511-515 - [c47]Shinya Kubota, Minoru Watanabe:
A nine-context programmable optically reconfigurable gate array with semiconductor lasers. ACM Great Lakes Symposium on VLSI 2009: 269-274 - [c46]Mao Nakajima, Minoru Watanabe:
A 13.75 ns Holographic Reconfiguration of an Optically Differential Reconfigurable Gate Array. IIH-MSP 2009: 852-855 - [c45]Mao Nakajima, Minoru Watanabe:
Fast Reconfiguration Experiments of an Optically Differential Reconfigurable Gate Array with Nine Configuration Contexts. ISCAS 2009: 2013-2016 - [c44]Shinichi Kato, Minoru Watanabe:
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. SAMOS 2009: 139-148 - 2008
- [c43]Kouhi Shinohara, Minoru Watanabe:
A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations. AHS 2008: 114-121 - [c42]Mao Nakajima, Minoru Watanabe:
Dynamic holographic reconfiguration on a four-context ODRGA. ASAP 2008: 173-178 - [c41]Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe:
MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA 2008: 222-228 - [c40]Mao Nakajima, Minoru Watanabe:
A 770ns Holographic Reconfiguration of a Four-Context DORGA. ERSA 2008: 289-292 - [c39]Takayuki Mabuchi, Minoru Watanabe:
An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays. FPT 2008: 289-292 - [c38]Mao Nakajima, Minoru Watanabe:
An 11, 424-gate dynamic optically reconfigurable gate array VLSI. FPT 2008: 293-296 - [c37]Shinichi Kato, Minoru Watanabe:
Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI. FPT 2008: 377-380 - [c36]Mao Nakajima, Daisaku Seto, Minoru Watanabe:
A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. IPDPS 2008: 1-6 - [c35]Kouhi Shinohara, Minoru Watanabe:
Defect tolerance of holographic configurations in ORGAs. IPDPS 2008: 1-8 - [c34]Daisaku Seto, Minoru Watanabe:
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. ISVLSI 2008: 511-514 - [c33]Daisaku Seto, Minoru Watanabe:
Analysis of retention time under multi-configuration on a DORGA. SoCC 2008: 131-134 - [c32]Naoki Yamaguchi, Minoru Watanabe:
An Optical Reconfiguration System with Four Contexts. VLSI Design 2008: 601-606 - [c31]Minoru Watanabe, Naoki Yamaguchi:
An Acceleration and Optimization Method for Optical Reconfiguration. VLSI Design 2008: 607-612 - 2007
- [c30]Minoru Watanabe, Fuminori Kobayashi:
A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ASP-DAC 2007: 124-125 - [c29]Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi:
272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA 2007: 259-264 - [c28]Minoru Watanabe:
Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. ERSA 2007: 291-294 - [c27]Daisaku Seto, Minoru Watanabe:
Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. FPT 2007: 265-268 - [c26]Mao Nakajima, Minoru Watanabe:
A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array. FPT 2007: 297-300 - [c25]Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi:
A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS 2007: 1-7 - [c24]Minoru Watanabe, Fuminori Kobayashi:
Holographic memory reconfigurable VLSI. ISCAS 2007: 401-404 - [c23]Minoru Watanabe:
An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. SoCC 2007: 75-78 - 2006
- [c22]Minoru Watanabe, Fuminori Kobayashi:
Optically Reconfigurable Gate Arrays vs. ASICs. APCCAS 2006: 1164-1167 - [c21]Minoru Watanabe, Fuminori Kobayashi:
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC 2006: 268-273 - [c20]Minoru Watanabe, Fuminori Kobayashi:
A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC 2006: 108-109 - [c19]Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi:
Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA 2006: 198-206 - [c18]Minoru Watanabe, Fuminori Kobayashi:
Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA 2006: 237-238 - [c17]Minoru Watanabe, Fuminori Kobayashi:
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA 2006: 239-240 - [c16]Minoru Watanabe, Fuminori Kobayashi:
A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL 2006: 1-6 - [c15]Minoru Watanabe, Fuminori Kobayashi:
Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS 2006 - [c14]Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi:
An optically differential reconfigurable gate array with a holographic memory. IPDPS 2006 - 2005
- [c13]Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi:
Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT 2005: 287-288 - [c12]Minoru Watanabe, Fuminori Kobayashi:
A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT 2005: 297-298 - [c11]Minoru Watanabe, Fuminori Kobayashi:
An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS 2005 - [c10]Minoru Watanabe, Fuminori Kobayashi:
A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) 2005: 1214-1217 - [c9]Minoru Watanabe, Fuminori Kobayashi:
An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI 2005: 136-141 - [c8]Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi:
Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI 2005: 274-275 - 2004
- [c7]Minoru Watanabe, Fuminori Kobayashi:
Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA 2004: 299-302 - [c6]Minoru Watanabe, Fuminori Kobayashi:
Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA 2004: 311 - [c5]Minoru Watanabe, Fuminori Kobayashi:
A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL 2004: 261-269 - [c4]Minoru Watanabe, Fuminori Kobayashi:
An optically differential reconfigurable gate array using a 0.18 μm CMOS process. SoCC 2004: 281-284 - [c3]Minoru Watanabe, Fuminori Kobayashi:
An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design 2004: 735- - 2003
- [j1]Takashi Sotohebo, Minoru Watanabe, Funtinori Kobayashi:
An FPGA Implementation of Finite Physical Quantity Neural Network. J. Robotics Mechatronics 15(2): 136-142 (2003) - [c2]Minoru Watanabe, Fuminori Kobayashi:
An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS 2003: 188 - 2002
- [c1]Minoru Watanabe, Fuminori Kobayashi:
An optically differential reconfigurable gate array and its power consumption estimation. FPT 2002: 197-202
Coauthor Index
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