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Takashi Yoza

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2010 – 2019

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2014
[c5]
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Takashi Yoza, Minoru Watanabe:
Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation. ARC 2014: 156-166
2013
[c4]
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Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe:
FPGA Blokus Duo Solver using a massively parallel architecture. FPT 2013: 494-497
2012
[c3]
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Takashi Yoza, Minoru Watanabe:
A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. AHS 2012: 92-98
[c2]
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Takashi Yoza, Minoru Watanabe:
A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. FPL 2012: 361-366
2011
[c1]
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Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe:
An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT 2011: 1-4

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