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2020 – today
- 2024
[j126]Chua-Chin Wang
, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador:
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. 43(6): 3376-3395 (2024)- [j125]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Pradyumna Vellanki:
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic. Integr. 98: 102234 (2024) - [j124]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo:
A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. 147: 106167 (2024) - [j123]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Bo-Hao Liao, Pradyumna Vellanki, Tzung-Je Lee:
A 1-6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD. Microelectron. J. 151: 106355 (2024) - [j122]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Jhih-Ying Ke, Cheng-Yao Lo, Tzung-Je Lee, Lean Karlo Santos Tolentino:
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4961-4972 (2024) - [j121]Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 972-976 (2024) - [c133]Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS 2024: 85-89 - [c132]Cheng-Yao Lo, Lean Karlo Santos Tolentino, Jhih-Ying Ke, Jeffrey S. Walling, Yang Yi, Chua-Chin Wang:
A 266.7 TOPS/W Computing-in Memory Using Single-Ended 6T 4-kb SRAM in 16-nm FinFET CMOS Process. AICAS 2024: 90-94 - [c131]Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS 2024: 95-99 - [c130]Oliver Lexter July A. Jose, Yun-Che Chang, Venkata Naveen Kolakaluri, Celso B. Co, Mitch Ming-Chi Chou, Chua-Chin Wang:
A 10-MHz 5-V On-chip 6-layer Multi-level Digital Transformer Using T18HVG2 Process. ISCAS 2024: 1-5 - [c129]Soumika Majumder, Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang:
A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. ISCAS 2024: 1-4 - 2023
- [j120]Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee:
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42(4): 2283-2304 (2023) - [j119]Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose:
A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices Syst. 17(2): 75-87 (2023) - [j118]Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang:
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90: 245-260 (2023) - [j117]Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang:
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3862-3866 (2023) - [c128]Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang:
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. APCCAS 2023: 50-54 - [c127]Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Jui-Min Kuo, Mitch Ming-Chi Chou, Chua-Chin Wang:
2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. APCCAS 2023: 266-270 - [c126]Jhih-Ying Ke, Lean Karlo S. Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process. APCCAS 2023: 271-275 - [c125]Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang:
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. ASICON 2023: 1-5 - [c124]Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang:
A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process. ICICDT 2023: 64-67 - [c123]Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang:
Matrix Phase Shift Based DPWM Technique To Achieve 90% Duty Cycle. ISCAS 2023: 1-4 - [c122]Oliver Lexter July A. Jose, Jui-Min Kuo, Venkata Naveen Kolakaluri, Chua-Chin Wang:
SiC MOSFET High Side Gate Driver Design Using HV CMOS Process. MWSCAS 2023: 45-49 - [c121]Venkata Naveen Kolakaluri, Oliver Lexter July A. Jose, Chua-Chin Wang:
A 99.6 % Duty Cycle High-Resolution DPWM Using Reconfiguring Decoder. MWSCAS 2023: 241-244 - 2022
- [j116]Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh:
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4860-4871 (2022) - [j115]Chia-Hung Yeh, Chu-Han Lin, Li-Wei Kang, Chih-Hsiang Huang, Min-Hui Lin, Chuan-Yu Chang, Chua-Chin Wang:
Lightweight Deep Neural Network for Joint Learning of Underwater Object Detection and Color Conversion. IEEE Trans. Neural Networks Learn. Syst. 33(11): 6129-6143 (2022) - [c120]Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Chua-Chin Wang:
A Novel Constant-pulse Scheme for Synchronous Half-bridge Converter Module. APCCAS 2022: 1-5 - [c119]Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu:
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS 2022: 46-49 - [c118]Jyoshnavi Akiri, Lean Karlo S. Tolentino, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang:
A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology. APCCAS 2022: 251-255 - [c117]Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang:
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. ICICDT 2022: 24-27 - [c116]Durga Srikanth Kamarajugadda, Oliver Lexter July A. Jose, Lung-Jieh Yang, Balasubramanian Esakki, Sivaperumal Sampath, Chua-Chin Wang:
A Low-Energy 8-bit CLA Realized by Single-Phase ANT Logic. ICICDT 2022: 28-31 - [c115]Tzung-Je Lee, Bo-Hao Liao, Chua-Chin Wang:
Wide Lock-in Range CDR with Modified DQFD and Coarse-fine Tuning Technique. ICICDT 2022: 61-64 - [c114]Li Lin, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 40-nm CMOS Wide Input Range and Variable Gain Time-Difference Amplifier Based on Current Source Architecture. ISCAS 2022: 2923-2927 - 2021
- [j114]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Yan-You Chou, Tzung-Je Lee:
2˟VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process. Circuits Syst. Signal Process. 40(6): 2824-2840 (2021) - [j113]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, I-Yu Huang, Yu-Cheng Lin, Tzung-Je Lee, Guan-Ru Chen:
High-Accuracy Impedance Read-out Circuit for BIA-type Biomedical Sensors. Circuits Syst. Signal Process. 40(9): 4187-4195 (2021) - [j112]Chua-Chin Wang, Pang-Yen Lou, Zong-You Hou, Hsiu-Chun Tsai:
0.7 % error rate 3A bidirectional current sensor using high voltage CMOS process. Microelectron. J. 114: 105127 (2021) - [j111]Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee:
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118: 105295 (2021) - [j110]Chua-Chin Wang:
Tutorial: Design of High-Speed Nano-Scale CMOS Mixed-Voltage Digital I/O Buffer With High Reliability to PVTL Variations. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 562-567 (2021) - [j109]Chua-Chin Wang, Chien-Ping Kuo:
200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3163-3166 (2021) - [j108]Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng:
A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. IEEE Trans. Circuits Syst. II Express Briefs 68(12): 3478-3482 (2021) - [j107]Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh:
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2172-2185 (2021) - [c113]Yu-Cheng Chou, Hsin-Hung Chen, Chau-Chang Wang, Hui-Min Chou, Chua-Chin Wang:
An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset. AICAS 2021: 1-4 - [c112]Tzung-Je Lee, Wen-Shou Yang, Chua-Chin Wang:
A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology. APCCAS 2021: 33-36 - [c111]Tzung-Je Lee, Wen-Jian Su, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment. APCCAS 2021: 153-156 - [c110]Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang:
A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. ISCAS 2021: 1-4 - [c109]Chua-Chin Wang, Chia-Yi Huang, Chia-Hung Yeh:
SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction. ISCAS 2021: 1-4 - [c108]Chua-Chin Wang, Chien-Ping Kuo:
67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. ISCAS 2021: 1-4 - [c107]Pang-Yen Lou, Yung-Yuan Ho, Chua-Chin Wang:
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer. ISOCC 2021: 1-2 - [c106]Pang-Yen Lou, Ying-Xuan Chen, Chua-Chin Wang:
On-chip CMOS Corner Detector Design for Panel Drivers. ISOCC 2021: 11-12 - 2020
- [j106]Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang:
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. 29(6): 2050088:1-2050088:17 (2020) - [j105]Chua-Chin Wang, Zong-You Hou, Deng-Shian Wang, Chia-Lung Hsieh:
A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry. J. Circuits Syst. Comput. 29(6): 2050095:1-2050095:18 (2020) - [j104]Tzung-Je Lee, Ssu-Wei Huang, Chua-Chin Wang:
A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique. IEEE Trans. Circuits Syst. 67-II(11): 2707-2711 (2020) - [j103]Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh:
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2069-2073 (2020) - [j102]Chua-Chin Wang, Nanang Sulistiyanto, Hsiang-Yu Shih, Yu-Cheng Lin, Wei Wang:
Power-effective ROM-less DDFS Design Approach with High SFDR Performance. J. Signal Process. Syst. 92(2): 213-224 (2020) - [c105]Chua-Chin Wang, Shao-Wei Lu:
100 MHz Random Number Generator Design Using Interleaved Metastable NAND/NOR Latches*. APCCAS 2020: 98-101 - [c104]Chua-Chin Wang, Chia-Yi Huang, Chu-Han Lin, Chia-Hung Yeh, Guan-Xian Liu, Yu-Cheng Chou:
3D-Modeling Dataset Augmentation for Underwater AUV Real-time Manipulations. APCCAS 2020: 145-148
2010 – 2019
- 2019
- [j101]Chua-Chin Wang, Tsung-Yi Tsai, Yu-Lin Deng, Tzung-Je Lee:
500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations. Circuits Syst. Signal Process. 38(2): 556-568 (2019) - [j100]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U. Fat Chio, Chua-Chin Wang:
A Slew Rate Variation Compensated 2× VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 116-120 (2019) - [j99]Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih:
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2464-2468 (2019) - [c103]Chun-Ting Chen, Tsung-Yi Tsai, Yi-Jen Chiu, Chua-Chin Wang:
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems. ASICON 2019: 1-4 - [c102]Pang-Yen Lou, Chien-Hua Chu, Chua-Chin Wang:
A Broken Line Detection Circuit for Multi-cell Li-ion Battery Module1. ICCE 2019: 1-2 - [c101]Nanang Sulistiyanto, Chua-Chin Wang, Robert Rieger:
A Low Frequency OTA Design with Temperature-Insensitive Variable Transconductance Using 180-nm CMOS Technology. ICICDT 2019: 1-4 - [c100]Tsung-Yi Tsai, Ting-Sheng Wang, Yi-Jen Chiu, Chua-Chin Wang:
A PVT Validation Phase-Lock Loop with Multi-Band VCO Applied in Closed-Loop FOGs. ICICDT 2019: 1-4 - [c99]Chua-Chin Wang, I-Ting Tseng:
Ultra Low Power Single-ended 6T SRAM Using 40 nm CMOS Technology. ICICDT 2019: 1-4 - [c98]Tzung-Je Lee, Chia-Hsin Hsu, Chua-Chin Wang:
High Efficiency Buck Converter with Wide Load Current Range using Dual-Mode of PWM and PSM. ISCAS 2019: 1-4 - [c97]Chua-Chin Wang, Guan-Xian Liu:
A 1.5A 88.6% Li-ion Battery Charger Design using Pulse Swallow Technique in Light Load. ISCAS 2019: 1-4 - 2018
- [j98]Chua-Chin Wang, Zong-You Hou, Chih-Lin Chen, Doron Shmilovitz:
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. Circuits Syst. Signal Process. 37(4): 1692-1703 (2018) - [j97]Chua-Chin Wang, Zong-You Hou, Jhih-Cheng You:
A High-Precision CMOS Temperature Sensor with Thermistor Linear Calibration in the (-5 °C, 120 °C) Temperature Range. Sensors 18(7): 2165 (2018) - [c96]Chua-Chin Wang, Zong-You Hou, Ssu-Wei Huang:
40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate. APCCAS 2018: 279-282 - [c95]Hao-Chun Huang, Deng-Shian Wang, Chua-Chin Wang:
A frequency-shift readout system with offset cancellation OPA for portable devices of marijuana detection. ICCE 2018: 1-2 - 2017
- [j96]Wen-Hui Huang, I-Yu Huang, Yu-Shan Tseng, Chia-Hsu Hsieh, Chua-Chin Wang:
A 19.38 dBm OIP3 gm-boosted up-conversion CMOS mixer for 5-6 GHz application. Microelectron. J. 60: 38-44 (2017) - [j95]Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang:
A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. Microelectron. J. 70: 107-116 (2017) - [j94]Je-Wei Lan, Chia-Hsu Hsieh, I-Yu Huang, Yu-Cheng Lin, Tsung-Yi Tsai, Chua-Chin Wang:
Highly Sensitive FPW-Based Microsystem for Rapid Detection of Tetrahydrocannabinol in Human Urine. Sensors 17(12): 2760 (2017) - [j93]Chua-Chin Wang, Zong-You Hou, Kai-Wei Ruan:
2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 812-816 (2017) - [j92]Tzung-Je Lee, Tsung-Yi Tsai, Wei Lin, U-Fat Chio, Chua-Chin Wang:
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3166-3174 (2017) - [c94]Zong-You Hou, Hsiu-Chun Tsai, Chua-Chin Wang:
High-voltage bidirectional current sensor. ASICON 2017: 1145-1146 - [c93]Zong-You Hou, Pang-Yen Lou, Chua-Chin Wang:
State of charge, state of health, and state of function monitoring for EV BMS. ICCE 2017: 310-311 - [c92]Zong-You Hou, Zong-Ying Ho, Jhih-Cheng You, Chua-Chin Wang:
A primary-side output current estimator with process compensator for flyback LED drivers. ISCAS 2017: 1-4 - [c91]Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang:
A pipeline ROM-less DDFS using equal-division interpolation. ISOCC 2017: 19-20 - [c90]Wei Wang, Yuan-Yuan Xu, Chua-Chin Wang:
Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. ISOCC 2017: 280-281 - 2016
- [j91]Chua-Chin Wang, Zong-You Hou, Wen-Je Lu, Sheng-Syong Wang:
High-voltage on-chip current sensor design and analysis for battery modules. IET Circuits Devices Syst. 10(6): 492-496 (2016) - [j90]Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen:
A Leakage Compensation Design for Low Supply Voltage SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1761-1769 (2016) - [c89]Chua-Chin Wang, Zong-You Hou, Teng-Wei Huang:
A flyback driver with adaptive switching frequency control for smart lighting1. ICCE 2016: 105-106 - [c88]Zong-You Hou, Teng-Wei Huang, Chua-Chin Wang:
On-chip accurate primary-side output current estimator for flyback LED driver control. ICICDT 2016: 1-4 - [c87]Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang:
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. ICICDT 2016: 1-4 - [c86]Tsung-Yi Tsai, Yu-Lin Teng, Chua-Chin Wang:
A nano-scale 2×VDD I/O buffer with encoded PV compensation technique. ISCAS 2016: 598-601 - [c85]Yu-Ting Tu, Deng-Shian Wang, Chua-Chin Wang:
An accurate phase shift detector using bulk voltage boosting technique for sensing applications. ISCAS 2016: 2110-2113 - [c84]Chua-Chin Wang, Chia-Lung Hsieh:
Disturb-free 5T loadless SRAM cell design with multi-vth transistors using 28 nm CMOS process. ISOCC 2016: 103-104 - [c83]Deng-Shian Wang, Yun-Shen Liu, Chua-Chin Wang:
A novel frequency-shift readout system for CEA concentration detection application. ISOCC 2016: 133-134 - 2015
- [j89]Chua-Chin Wang, Wen-Je Lu, Kai-Wei Juan, Wei Lin, Hsin-Yuan Tseng, Chun-Ying Juan:
Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology. Microelectron. J. 46(1): 1-11 (2015) - [j88]Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee:
A ±3.07% frequency variation clock generator implemented using HV CMOS process. Microelectron. J. 46(4): 285-290 (2015) - [j87]Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu:
Wide-range CTAT and PTAT sensors with second-order calibration for on-chip thermal monitoring. Microelectron. J. 46(9): 819-824 (2015) - [j86]Chua-Chin Wang, Tsung-Yi Tsai, Wen-Je Lu, Chih-Lin Chen, Yi-Lun Wu:
A 30 V rail-to-rail operational amplifier. Microelectron. J. 46(10): 911-915 (2015) - [j85]Chua-Chin Wang, Wen-Je Lu, Tsung-Yi Tsai:
Analysis of Calibrated On-Chip Temperature Sensor With Process Compensation for HV Chips. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 217-221 (2015) - [j84]Chua-Chin Wang, Chih-Lin Chen, Zong-You Hou, Yi Hu, Jam-Wem Lee, Wan-Yen Lin, Yi-Feng Chang, Chia-Wei Hsu, Ming-Hsiang Song:
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 752-760 (2015) - [j83]Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 244-253 (2015) - [c82]Chua-Chin Wang, Min-Yu Tseng:
10 Mbps high-voltage digital transciever on single die for 50 V voltage swing. ASICON 2015: 1-4 - [c81]Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A high-voltage Transceiver for electrical vehicle Battery Management Systems. ICCE 2015: 295-296 - [c80]Chua-Chin Wang, Tsung-Yi Tsai, Wei Lin:
A high-speed 2×VDD output buffer with PVTL detection using 40-nm CMOS technology. ICICDT 2015: 1-4 - [c79]Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang:
A wide range and high conversion gain power detector for frequency shift sensing applications. MWSCAS 2015: 1-4 - 2014
- [j82]Doron Shmilovitz, Shaul Ozeri, Chua-Chin Wang, Boaz Spivak:
Noninvasive Control of the Power Transferred to an Implanted Device by an Ultrasonic Transcutaneous Energy Transfer Link. IEEE Trans. Biomed. Eng. 61(4): 995-1004 (2014) - [j81]Chua-Chin Wang, Chih-Lin Chen, Gang-Neng Sung, Ching-Lin Wang, Chun-Ying Juan:
A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard. J. Signal Process. Syst. 74(2): 221-233 (2014) - [c78]Chua-Chin Wang, Deng-Shian Wang, Shiou-Ya Chen, Chia-Ming Chang:
A 20 GHz power detector with 176 mV/dB conversion gain. APCCAS 2014: 551-554 - [c77]Chua-Chin Wang, Wen-Je Lu, Min-Yu Tseng:
An all-digital battery capacity monitor using calibrated current estimation approach. APCCAS 2014: 563-566 - [c76]Tzung-Je Lee, Kai-Wei Ruan, Chua-Chin Wang:
32% Slew rate and 27% data rate improved 2×VDD output buffer using PVTL compensation. ICICDT 2014: 1-4 - [c75]Chua-Chin Wang, Wen-Je Lu, Sheng-Syong Wang:
An on-chip high-voltage current sensor for battery module monitoring. ICICDT 2014: 1-4 - [c74]Chua-Chin Wang, Wen-Je Lu, Tzu-Chao Wu, Chun-Ying Juan:
A CMOS wide-range temperature sensor with process compensation and second-order calibration for Battery Management Systems. ISCAS 2014: 586-589 - [c73]Chua-Chin Wang, Chiang-Hsiang Liao, Sih-Yu Chen:
A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process. ISCAS 2014: 1126-1129 - 2013
- [j80]Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Gang-Neng Sung, Tai-Hao Yeh, Chun-Ying Juan:
A low-power transceiver design for FlexRay-based communication systems. Microelectron. J. 44(4): 359-366 (2013) - [j79]Chua-Chin Wang, Wen-Je Lu, Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chun-Ying Juan:
A 2×VDD output buffer with PVT detector for slew rate compensation. Microelectron. J. 44(5): 393-399 (2013) - [j78]Chua-Chin Wang, Tzu-Chiao Sung, Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang:
A Protein Concentration Measurement System Using a Flexural Plate-Wave Frequency-Shift Readout Technique. Sensors 13(1): 86-105 (2013) - [j77]Chua-Chin Wang, Chih-Lin Chen, Hsin-Yuan Tseng, Hsiao-Han Hou, Chun-Ying Juan:
A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 116-124 (2013) - [j76]Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Hsin-Yuan Tseng, Jen-Wei Liu, Chun-Ying Juan:
On-Chip Process and Temperature Monitor for Self-Adjusting Slew Rate Control of 2, ×, VDD Output Buffers. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1432-1440 (2013) - [c72]Chih-Lin Chen, Zong-You Hou, Sheng-Chih Lin, Chua-Chin Wang:
A delay-based transceiver with over-current protection for ECU nodes in automobile FlexRay systems. ICCE 2013: 610-611 - [c71]Chih-Lin Chen, Yi-Lun Wu, Chun-Ying Juan, Chua-Chin Wang:
High voltage operational amplifier and high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. ICICDT 2013: 97-100 - [c70]Chua-Chin Wang, Wen-Je Lu, Hsin-Yuan Tseng:
A high-speed 2×VDD output buffer with PVT detection using 40-nm CMOS technology. ISCAS 2013: 2079-2082 - 2012
- [j75]Shang-Hsien Yang, Chua-Chin Wang:
Feed-forward Output Swing Prediction AGC design with Parallel-Detect Singular-Store Peak Detector. Microelectron. J. 43(4): 250-256 (2012) - [j74]Shang-Hsien Yang, Chua-Chin Wang:
A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers. Microelectron. J. 43(4): 274-279 (2012) - [j73]Shang-Hsien Yang, Jen-Wei Liu, Chua-Chin Wang:
A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1588-1597 (2012) - [j72]Chua-Chin Wang, Chia-Hao Hsu, Gang-Neng Sung, Yu-Cheng Lu:
A Signed Array Multiplier with Bypassing Logic. J. Signal Process. Syst. 66(2): 87-92 (2012) - [c69]Tzung-Je Lee, Wen-Je Lu, Wei-Chih Hsiao, Chua-Chin Wang:
Linear programmable gain amplifier using reconfiguration local-feedback transconductors. APCCAS 2012: 228-231 - [c68]Chua-Chin Wang, Tzu-Chiao Sung, Yihong Wu, Chia-Hao Hsu, Doron Shmilovitz:
A reconfigurable 16-channel HV stimulator ASIC for Spinal Cord Stimulation systems. APCCAS 2012: 300-303 - [c67]Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Chun-Ying Juan:
Configurable Active Star design for automobile FlexRay systems. ICCE 2012: 301-302 - [c66]Gang-Neng Sung, Chun-Ming Huang, Chua-Chin Wang:
A PLC transceiver design of in-vehicle power line in FlexRay-based automotive communication systems. ICCE 2012: 309-310 - [c65]Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang, Chua-Chin Wang:
A fast FPW allergy analyzer prototype for point of care (POC). ICCE 2012: 540-541 - [c64]Chih-Lin Chen, Yi Hu, Wayne Luo, Chua-Chin Wang, Chun-Ying Juan:
A high voltage analog multiplexer with digital calibration for battery management systems. ICICDT 2012: 1-4 - [c63]Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang:
On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers. ICICDT 2012: 1-4 - [c62]Sih-Yu Chen, Chua-Chin Wang:
Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process. ICICDT 2012: 1-4 - [c61]Tzung-Je Lee, Doron Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang:
Temperature and process compensated clock generator using feedback TPC bias. ICICDT 2012: 1-4 - [c60]Chih-Lin Chen, Sheng-Chih Lin, Chua-Chin Wang, Chun-Ying Juan:
A digital over-temperature protector for FlexRay systems. ISCAS 2012: 1991-1994 - [c59]Chua-Chin Wang, Chia-Hao Hsu, Yue-Da Tsai, Yun-Chi Chen, Ming-Chih Lee, I-Yu Huang:
A fast FPW-based protein concentration measurement system. ISCAS 2012: 2389-2392 - [c58]Shang-Hsien Yang, Chua-Chin Wang:
Feed-forward Output Swing Prediction AGC with Parallel-Detect Singular-Store Peak Detector. ISCAS 2012: 2965-2968 - [c57]Chih-Lin Chen, Deng-Shian Wang, Jie-Jyun Li, Chua-Chin Wang:
A Battery Interconnect Module with high voltage transceiver using 0.25 µm 60V BCD process for Battery Management Systems. ISOCC 2012: 1-4 - [c56]Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang:
A slew rate self-adjusting 2×VDD output buffer With PVT compensation. VLSI-DAT 2012: 1-4 - 2011
- [j71]Chua-Chin Wang, Chih-Lin Chen, Gang-Neng Sung, Ching-Lin Wang:
A high-efficiency DC-DC buck converter for sub-2×VDD power supply. Microelectron. J. 42(5): 709-717 (2011) - [j70]Chua-Chin Wang, Ron-Chi Kuo, Tung-Han Tsai:
A high precision low dropout regulator with nested feedback loops. Microelectron. J. 42(7): 966-971 (2011) - [j69]Chia-Hao Hsu, Shao-Bin Tseng, Yi-Jie Hsieh, Chua-Chin Wang:
One-Time-Implantable Spinal Cord Stimulation System Prototype. IEEE Trans. Biomed. Circuits Syst. 5(5): 490-498 (2011) - [j68]Chua-Chin Wang, Chia-Hao Hsu, Szu-Chia Liao, Yi-Cheng Liu:
A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1481-1485 (2011) - [j67]Chua-Chin Wang, Chia-Hao Hsu, Chia-Chuan Lee, Jian-Ming Huang:
A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset. J. Signal Process. Syst. 64(3): 351-359 (2011) - [c55]Chua-Chin Wang, Chih-Lin Chen, Tai-Hao Yeh, Yi Hu, Gang-Neng Sung:
A high speed transceiver front-end design with fault detection for FlexRay-based automotive communication systems. ISCAS 2011: 434-437 - [c54]Shang-Hsien Yang, Jen-Wei Liu, Yihong Wu, Deng-Sian Wang, Chua-Chin Wang:
A high voltage battery charger with smooth charge mode transition in BCD process. ISCAS 2011: 813-816 - [c53]Shang-Hsien Yang, Chua-Chin Wang:
A 48-dB dynamic gain range/stage linear-in-dB low power Variable Gain Amplifier for direct-conversion receivers. ISOCC 2011: 182-1 - 2010
- [j66]Chua-Chin Wang, Gang-Neng Sung, Jian-Ming Huang, Lung-Hsuan Lee, Chih-Peng Li:
A low-power 2.45 GHz WPAN modulator/demodulator. Microelectron. J. 41(2-3): 150-154 (2010) - [j65]Chua-Chin Wang, Chia-Hao Hsu, Chi-Chun Huang, Jun-Han Wu:
A Self-Disabled Sensing Technique for Content-Addressable Memories. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 31-35 (2010) - [j64]Chi-Chun Huang, Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang:
(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(2): 126-130 (2010) - [j63]Chua-Chin Wang, Gang-Neng Sung, Po-Cheng Chen, Chin-Long Wey:
A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(2): 460-470 (2010) - [j62]Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Doron Shmilovitz:
Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications. IEEE Trans. Circuits Syst. II Express Briefs 57-II(4): 265-269 (2010) - [j61]Chua-Chin Wang, Felix Lustenberger, Yehia Massoud, Wouter A. Serdijn:
Guest Editorial Special Issue on ISCAS 2009. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(5): 953-955 (2010) - [j60]Chua-Chin Wang, Chia-Hao Hsu, Yi-Cheng Liu:
A 1/2 times hbox VDD to 3 times hbox VDD Bidirectional I/O Buffer With a Dynamic Gate Bias Generator. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1642-1653 (2010) - [j59]Gang-Neng Sung, Szu-Chia Liao, Jian-Ming Huang, Yu-Cheng Lu, Chua-Chin Wang:
All-Digital Frequency Synthesizer Using a Flying Adder. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 597-601 (2010) - [j58]Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu:
0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 612-616 (2010) - [j57]Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen:
Energy-Efficient Double-Edge Triggered Flip-Flop. J. Signal Process. Syst. 61(3): 347-352 (2010) - [c52]Ron-Chi Kuo, Hsiao-Han Hou, Chua-Chin Wang:
A PCI166-compatible 3×VDD-tolerant mixed-voltage I/O buffer. APCCAS 2010: 320-323 - [c51]Ron-Chi Kuo, Tung-Han Tsai, Yi-Jie Hsieh, Chua-Chin Wang:
A high precision low dropout regulator with nested feedback loops. APCCAS 2010: 664-667 - [c50]Chua-Chin Wang, Chi-Chun Huang, Yi-Cheng Liu, Victor Pikov, Doron Shmilovitz:
A mini-invasive multi-function biomedical pressure measurement system ASIC. ISCAS 2010: 2936-2939 - [c49]Chua-Chin Wang, Szu-Chia Liao, Yi-Cheng Liu:
A 125-MHz wide-range mixed-voltage I/O buffer using gated Floating N-well circuit. ISCAS 2010: 3421-3424
2000 – 2009
- 2009
- [j56]Sen-Hung Wang, Chih-Peng Li, Chao-Tang Yu, Jian-Ming Huang, Chua-Chin Wang:
Baseband Receiver Design for the MBOA Ultra Wideband Wireless Personal Area Networks. IEICE Trans. Commun. 92-B(1): 143-149 (2009) - [j55]Tzung-Je Lee, Tieh-Yen Chang, Chua-Chin Wang:
Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(4): 763-772 (2009) - [j54]Chua-Chin Wang, Gang-Neng Sung:
Low-Power Multiplier Design Using a Bypassing Technique. J. Signal Process. Syst. 57(3): 331-338 (2009) - [c48]Chia-Hao Hsu, Gang-Neng Sung, Tuo-Yu Yao, Chun-Ying Juan, Yain-Reu Lin, Chua-Chin Wang:
Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology. ISCAS 2009: 389-392 - [c47]Shaul Ozeri, Doron Shmilovitz, Chua-Chin Wang:
A Drive Circuit for Piezoelectric Devices with Low Harmonics Content. ISCAS 2009: 1093-1096 - 2008
- [j53]Chua-Chin Wang, Gang-Neng Sung, Chi-Chun Huang, Ching-Li Lee, Tian-Hau Chen, Wun-Ji Lin, Ron Hu:
A 1.7-ns Access Time SRAM Using Variable Bulk Bias wordline-Controlled transistors. J. Circuits Syst. Comput. 17(5): 943-956 (2008) - [j52]Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Chien-Chih Hung, Li-Pin Lin:
A single-chip CMOS IF-band converter design for DVB-T receivers. Microelectron. J. 39(1): 117-129 (2008) - [j51]Chua-Chin Wang, Tzung-Je Lee, U. Fat Chio, Yu-Tzu Hsiao, Jia-Jin Chen:
A 570-kbps ASK demodulator without external capacitors for low-frequency wireless bio-implants. Microelectron. J. 39(1): 130-136 (2008) - [j50]Chua-Chin Wang, Chi-Chun Huang, Sheng-Lun Tseng:
A low-power ADPLL using feedback DCO quarterly disabled in time domain. Microelectron. J. 39(5): 832-840 (2008) - [j49]Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yung-Chin Lee, Weng-Jeng Wu:
A Mini-Invasive Long-Term Bladder Urine Pressure Measurement ASIC and System. IEEE Trans. Biomed. Circuits Syst. 2(1): 44-49 (2008) - [j48]Tzung-Je Lee, Ching-Li Lee, Yan-Jhin Ciou, Chi-Chun Huang, Chua-Chin Wang:
All-MOS ASK Demodulator for Low-Frequency Applications. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 474-478 (2008) - [j47]Chua-Chin Wang, Chi-Chun Huang, Ching-Li Lee, Tsai-Wen Cheng:
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic. IEEE Trans. Very Large Scale Integr. Syst. 16(5): 594-598 (2008) - [j46]Chua-Chin Wang, Chi-Chun Huang, Jian-Ming Huang, Chih-Yi Chang, Chih-Peng Li:
ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 936-939 (2008) - [j45]Tzung-Je Lee, Chua-Chin Wang:
A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators. VLSI Design 2008: 512946:1-512946:8 (2008) - [j44]Chua-Chin Wang, Gang-Neng Sung, Pai-Li Liu:
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection. J. Signal Process. Syst. 52(2): 127-135 (2008) - [c46]Chi-Chun Huang, Shou-Fu Yen, Chua-Chin Wang:
A Li-ion battery charging design for biomedical implants. APCCAS 2008: 400-403 - [c45]Chua-Chin Wang, Chia-Hao Hsu, Tuo-Yu Yao, Jian-Ming Huang:
A ROM-less DDFS using a nonlinear DAC with an error compensation current array. APCCAS 2008: 1632-1635 - [c44]Chi-Chun Huang, Jun-Han Wu, Chua-Chin Wang:
A self-disable sense technique with differential NAND cell for content-addressable memories. ICECS 2008: 590-593 - [c43]Gang-Neng Sung, Chun-Ying Juan, Chua-Chin Wang:
A 32-bit carry lookahead adder design using complementary all-N-transistor logic. ICECS 2008: 706-709 - [c42]Tzung-Je Lee, Wei-Chih Chang, Chua-Chin Wang:
Mixed-voltage I/O buffer using 0.35 μm CMOS technology. ICECS 2008: 850-853 - [c41]Jian-Ming Huang, Chia-Chuan Lee, Chua-Chin Wang:
A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation. ICECS 2008: 1018-1021 - [c40]Tung-Han Tsai, Chin-Lin Chen, Ching-Li Lee, Chua-Chin Wang:
Power-saving nano-scale DRAMs with an adaptive refreshing clock generator. ISCAS 2008: 612-615 - [c39]Chua-Chin Wang, Chi-Chun Huang, Jun-Han Wu, I-Yu Huang:
A mini-invasive multi-function bladder urine pressure measurement system. ISCAS 2008: 3174-3177 - [c38]Gang-Neng Sung, Yan-Jhin Ciou, Chua-Chin Wang:
A power-aware 2-dimensional bypassing multiplier using cell-based design flow. ISCAS 2008: 3338-3341 - 2007
- [j43]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator. Microelectron. J. 38(2): 197-202 (2007) - [j42]Chua-Chin Wang, Gang-Neng Sung, Jian-Ming Huang, Li-Ping Lin:
An 80MHz PLL with 72.7ps peak-to-peak jitter. Microelectron. J. 38(6-7): 716-721 (2007) - [j41]Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin:
A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 1069-1076 (2007) - [c37]Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yung-Chin Lee, Wen-Jen Wu:
An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation Amplifier. ISCAS 2007: 2383-2386 - [c36]Chua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng:
A Low-power Sensorless Inverter Controller of Brushless DC Motors. ISCAS 2007: 2435-2438 - 2006
- [j40]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
An All-MOS High-Linearity Voltage-to-Frequency Converter Chip With 520-kHz/V Sensitivity. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 744-747 (2006) - [j39]Chua-Chin Wang, Jian-Ming Huang, Yih-Long Tseng, Wun-Ji Lin, Ron Hu:
Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1143-1147 (2006) - [j38]Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, Jin-Fon Huang:
Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1318-1322 (2006) - [j37]Chua-Chin Wang, Tzung-Je Lee, Hoi Kam Lo, Shih-Ping Lin, Ron Hu:
High-sensitivity and high-mobility compact DVB-T receiver for in-car entertainment. IEEE Trans. Consumer Electron. 52(1): 21-25 (2006) - [c35]Chua-Chin Wang, Tzung-Je Lee, Chih-Chen Li, Ron Hu:
An All-MOS High Linearity Voltage-to-Frequency Converter Chip with 520 KHz/V Sensitivity. APCCAS 2006: 267-270 - [c34]Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, Cheng-Mu Wu, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng, Jia-Jin Chen:
An Implantable SOC Chip for Micro-stimulating and Neural Signal Recording. APCCAS 2006: 682-685 - [c33]Chua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Kuan-Wen Fang:
A 140-dB CMRR Low-noise Instrumentation Amplifier for Neural Signal Sensing. APCCAS 2006: 696-699 - [c32]Chua-Chin Wang, Chi-Chun Huang, Tzung-Je Lee, U. Fat Chio:
A Linear LDO Regulator with Modified NMCF Frequency Compensation Independent of Off-chip Capacitor and ESR. APCCAS 2006: 880-883 - [c31]Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ching-Li Lee, Cheng-Mu Wu, Ju-Ya Chen:
A Low-power 4-T SAM Design for OFDM Demodulators in DVB Receiversers. APCCAS 2006: 1112-1115 - [c30]Chua-Chin Wang, Gang-Neng Sung, Ming-Kai Chang, Ying-Yu Shen:
Engery-Efficient Double-Edge Triggered Flip-Flop Design. APCCAS 2006: 1791-1794 - [c29]Chua-Chin Wang, Gang-Neng Sung, Jia-Hao Li:
Codec Design for Variable-Length to Fixed-Length Data Conversion for H.263. IIH-MSP 2006: 483-486 - [c28]Chua-Chin Wang, Jian-Ming Huang, Chih-Yi Chang, Kuang-Ting Cheng, Chih-Peng Li:
A 6.57 mW ZigBee transceiver for 868/915 MHz band. ISCAS 2006 - [c27]Chua-Chin Wang, Ching-Li Lee, Wun-Ji Lin:
A 4-Kb low power 4-T SRAM design with negative word-line gate drive. ISCAS 2006 - [c26]Chua-Chin Wang, Gang-Neng Sung:
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. ISVLSI 2006: 405-410 - 2005
- [j36]Chua-Chin Wang, Jian-Ming Huang, Hon-Chen Cheng, Ron Hu:
Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator. IEEE J. Solid State Circuits 40(6): 1360-1365 (2005) - [j35]Chua-Chin Wang, Ching-Li Lee, Yih-Long Tseng, Chiuan-Shian Chen, Ron Hu:
Low-Power Small-Area Digital I/O Cell. IEEE Trans. Circuits Syst. II Express Briefs 52-II(8): 508-511 (2005) - [j34]Chua-Chin Wang, Jian-Ming Huang, Hsian-Chang Cheng:
A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers. IEEE Trans. Consumer Electron. 51(1): 28-32 (2005) - [j33]Chua-Chin Wang, Ching-Li Lee, Ming-Kai Chang:
Low-cost video decoder with 2D2L comb filter for NTSC digital TVs. IEEE Trans. Consumer Electron. 51(2): 694-698 (2005) - [j32]Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu:
A temperature-insensitive self-recharging circuitry used in DRAMs. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 405-408 (2005) - [j31]Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh:
A multiparameter implantable microstimulator SOC. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1399-1402 (2005) - [c25]Chua-Chin Wang, Ching-Li Lee, Li-Ping Lin, Yih-Long Tseng:
Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. ISCAS (1) 2005: 356-359 - 2004
- [j30]Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Chih-Chen Li, Ron Hu:
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 895-900 (2004) - [j29]Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu:
A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 901-909 (2004) - [j28]Chua-Chin Wang, Yih-Long Tseng, Hsien-Chih She, Ron Hu:
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1377-1381 (2004) - [c24]Chua-Chin Wang, Ya-Hsin Hsueh, U. Fat Chio, Yu-Tzu Hsiao:
A C-less ASK demodulator for implantable neural interfacing chips. ISCAS (4) 2004: 57-60 - [c23]Chua-Chin Wang, Yih-Long Tseng, Tzung-Je Lee, Ron Hu:
High-PSR bias circuitry for NTSC sync separation. ISCAS (1) 2004: 329-332 - [c22]Chua-Chin Wang, Ya-Hsin Hsueh, Sen-Fu Hong, Rong-Sui Kao:
A phase-adjustable negative phase shifter using a single-shot locking method. ISCAS (2) 2004: 933-936 - 2003
- [j27]Chua-Chin Wang, Po-Ming Lee, Kuo-Long Chen:
An SRAM design using dual threshold voltage transistors and low-power quenchers. IEEE J. Solid State Circuits 38(10): 1712-1720 (2003) - [j26]Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen:
An area-saving decoder structure for ROMs. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 581-589 (2003) - [j25]Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang:
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 737-740 (2003) - [c21]Chua-Chin Wang, Yih-Long Tseng, Tian-Hau Chen, Ron Hu:
Dual-polarity high voltage generator design for non-volatile memories. ICECS 2003: 248-251 - [c20]Chua-Chin Wang, Ya-Hsin Hsueh, Ting-Wan Kuo, Ron Hu:
A boosted wordline voltage generator for low-voltage memories. ICECS 2003: 806-809 - 2002
- [j24]Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu:
Image Processing Techniques for Wafer Defect Cluster Identification. IEEE Des. Test Comput. 19(2): 44-48 (2002) - [j23]Chua-Chin Wang, Ya-Hsin Hsueh, Chiuan-Shian Chen, Jih-Fon Huang:
A low-cost plasma display panel data dispatcher for image enhancement. IEEE Trans. Consumer Electron. 48(4): 997-1003 (2002) - [j22]Chua-Chin Wang, Ya-Hsin Hsueh, Shao-Ku Huang:
An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method. VLSI Design 14(2): 193-202 (2002) - [j21]Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen:
Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design 14(4): 373-381 (2002) - [j20]Chua-Chin Wang, Po-Ming Lee, Chenn-Jung Huang:
Improved Design of C2PL 3-2 Compressors for Inner Product Processing. VLSI Design 14(4): 383-388 (2002) - [j19]Chua-Chin Wang, Ya-Hsin Hsueh, Hsin-Long Wu, Chih-Feng Wu:
A Fast Dynamic 64-bit Comparator with Small Transistor Count. VLSI Design 14(4): 389-395 (2002) - [c19]Chua-Chin Wang, Hsien-Chih She, Ron Hu:
A ROM-less direct digital frequency synthesizer by using trigonometric quadruple angle formula. ICECS 2002: 65-68 - [c18]Chua-Chin Wang, Hsien-Chih She, Ron Hu:
A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. ICECS 2002: 69-72 - [c17]Chua-Chin Wang, Po-Ming Lee, Kuo-Long Chen:
6-T SRAM using dual threshold voltage transistors and low-power quenchers. ICECS 2002: 827-830 - 2001
- [j18]Chenn-Jung Huang, Wei Kuang Lai, Chua-Chin Wang, Yu-Jyr Jin, Hsin Wei Chen:
A ratioed channel assignment scheme for initial and handoff calls in mobile cellular systems. Comput. Commun. 24(3-4): 308-318 (2001) - [j17]Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien:
Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. J. Inf. Sci. Eng. 17(2): 313-324 (2001) - [c16]Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien:
Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs. ICECS 2001: 233-236 - [c15]Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen:
An area-saving 3-dimensional decoder structure for ROMs. ICECS 2001: 573-576 - [c14]Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang:
Design of a cycle-efficient 64b/32b integer divider using a table-sharing method. ICECS 2001: 921-924 - [c13]Chua-Chin Wang, Yih-Long Tseng, Rong-Sui Kao:
A 1.0 GHz clock generator design with a negative delay using a single-shot locking method. ICECS 2001: 1123-1126 - [c12]Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang:
A 1.25 GHz 32-bit tree-structured carry lookahead adder. ISCAS (4) 2001: 80-83 - 2000
- [j16]Chua-Chin Wang, Cheng-Fa Tsai:
Fuzzy data processing using polynomial bidirectional hetero-associative network. Inf. Sci. 125(1-4): 167-179 (2000) - [j15]Chua-Chin Wang, Chi-Feng Wu, Rain-Ted Hwang, Chia-Hsiung Kao:
Single-ended SRAM with high test coverage and short test time. IEEE J. Solid State Circuits 35(1): 114-118 (2000) - [j14]Chua-Chin Wang, Chenn-Jung Huang, Shiou-Ming Hwang:
A deterministic capacity-finding method for multi-valued exponential BAM. IEEE Trans. Syst. Man Cybern. Part A 30(6): 817-819 (2000) - [j13]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design 11(2): 107-113 (2000) - [j12]Chua-Chin Wang, Chenn-Jung Huang, I-Yen Chang:
Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library. VLSI Design 11(4): 331-338 (2000) - [j11]Chua-Chin Wang, Chenn-Jung Huang, Po-Ming Lee:
Design and Analysis of Digital Ratioed Compressors for Inner Product Processing. VLSI Design 11(4): 353-361 (2000) - [c11]Chua-Chin Wang, Cheng-Fa Tsai:
A Novel Neural Architecture with High Storage Capacity. IJCNN (5) 2000: 617-621 - [c10]Chua-Chin Wang, Po-Ming Lee, Chenn-Jung Hunng:
Improved design of C2PL 3-2 compressors with less transistor count. ISCAS 2000: 61-64 - [c9]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
Design of an inter-plane circuit for clocked PLAs. ISCAS 2000: 281-284 - [c8]Chua-Chin Wang, Hsin-Long Wu, Chih-Feng Wu:
A fast dynamic 64-bit comparator with small transistor count. ISCAS 2000: 545-548
1990 – 1999
- 1999
- [c7]Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-Lin Wu:
Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. ICECS 1999: 1217-1220 - [c6]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) 1999: 528-531 - [c5]Chua-Chin Wang, Cheng-Fa Tsai:
Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator. ISCAS (5) 1999: 583-586 - 1998
- [j10]Chua-Chin Wang, Hon-Son Don:
The Majority Theorem of Centralized Multiple BAMs Networks. Inf. Sci. 110(3-4): 179-193 (1998) - [j9]Chua-Chin Wang, Chang-Rong Tsai:
Data compression by the recursive algorithm of exponential bidirectional associative memory. IEEE Trans. Syst. Man Cybern. Part B 28(2): 125-134 (1998) - [c4]Chua-Chin Wang, Cheng-Fa Tsai:
Fuzzy data recall using polynomial bidirectional hetero-correlator. SMC 1998: 1940-1945 - 1997
- [j8]Chua-Chin Wang, Chih-Lwan Fan:
Digital Design of Discrete Exponential Bidirectional Associative Memory. J. VLSI Signal Process. 15(3): 247-257 (1997) - 1996
- [j7]Chua-Chin Wang:
Practical Capacity and Attraction Radix Analysis of Exponential Bidirectional Associative Memory. J. Inf. Sci. Eng. 12(4): 511-523 (1996) - [j6]Chua-Chin Wang, Shiou-Ming Hwang, Jyh-Ping Lee:
Capacity analysis of the asymptotically stable multi-valued exponential bidirectional associative memory. IEEE Trans. Syst. Man Cybern. Part B 26(5): 733-743 (1996) - 1995
- [j5]Chua-Chin Wang, Hon-Son Don:
An analysis of high-capacity discrete exponential BAM. IEEE Trans. Neural Networks 6(2): 492-496 (1995) - [j4]Chua-Chin Wang, Jyh-Ping Lee:
The decision-making properties of discrete multiple exponential bidirectional associative memories. IEEE Trans. Neural Networks 6(4): 993-999 (1995) - [c3]Chua-Chin Wang, In-Hau Horng:
Realization of bidirectional associative memory using a pseudo-parallel searching approach. ICNN 1995: 1502-1507 - [c2]Chua-Chin Wang, Chih-Lwan Fan:
Digital design of discrete exponential bidirectional associative memory. ICNN 1995: 2031-2036 - [c1]Chua-Chin Wang, Jeng-Ming Wu:
Analysis and Current-Mode Implementation of Asymptotically Stable Exponential Bidirectional Associative Memory. ISCAS 1995: 421-424 - 1994
- [j3]Chua-Chin Wang, Hon-Son Don:
A Polar Model for Evidential Reasoning. Inf. Sci. 77(3-4): 195-226 (1994) - [j2]Chua-Chin Wang, Hon-Son Don:
A Modified Measure for Fuzzy Subsethood. Inf. Sci. 79(3-4): 223-232 (1994) - [j1]Chua-Chin Wang, Hon-Son Don:
A robust continuous model for evidential reasoning. J. Intell. Robotic Syst. 10(2): 147-171 (1994)
Coauthor Index
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