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"2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate ..."

Chua-Chin Wang et al. (2020)

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DOI: 10.1142/S0218126620500887

access: closed

type: Journal Article

metadata version: 2020-11-06

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  - https://dblp.org/rec/journals/jcsc/WangHDCW20
Chua-Chin Wang, Zong-You Hou, Yu-Lin Deng, U. Fat Chio, Wei Wang:
2-GHz 2×VDD 28-nm CMOS Digital Output Buffer with Slew Rate Auto-Adjustment Against Process and Voltage Variations. J. Circuits Syst. Comput. 29(6): 2050088:1-2050088:17 (2020)

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