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ORCIDRalph Gerard B. Sangalang
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2020 – today
- 2024
[j10]Chua-Chin Wang
, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador:
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process. Circuits Syst. Signal Process. 43(6): 3376-3395 (2024)- [j9]Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo:
A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectron. J. 147: 106167 (2024) - [j8]Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 972-976 (2024) - [c8]Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS 2024: 85-89 - 2023
- [j7]Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee:
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Syst. Signal Process. 42(4): 2283-2304 (2023) - [j6]Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose:
A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices Syst. 17(2): 75-87 (2023) - [j5]Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang:
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process. Integr. 90: 245-260 (2023) - [j4]Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang:
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3862-3866 (2023) - [c7]Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang:
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. APCCAS 2023: 50-54 - [c6]Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang:
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS. ASICON 2023: 1-5 - [c5]Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang:
A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process. ICICDT 2023: 64-67 - [c4]Leinard C. Lontoc, Marjorie H. Basco, Vannesa Ann P. Sulit, Genesis Aubrey M. Magpantay, Mirasol C. Dilay, Ralph Gerard B. Sangalang:
Developing an LTE Learning Material: Experiences from a University in a Developing Country. ICIT 2023: 295-299 - [c3]Khryzz Lyden G. Cueto, Ricky Mae V. Santos, Claudette Jane C. Hilario, John Carl V. Aggari, Ralph Gerard B. Sangalang:
FPGA-Based Radio Transceiver Using the TV White Space for Disaster Response Operation. ICIT 2023: 300-304 - 2022
- [j3]Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh:
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4860-4871 (2022) - [c2]Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu:
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. APCCAS 2022: 46-49 - [c1]Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang:
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. ICICDT 2022: 24-27 - 2021
- [j2]Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee:
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS. Microelectron. J. 118: 105295 (2021) - [j1]Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng:
A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. IEEE Trans. Circuits Syst. II Express Briefs 68(12): 3478-3482 (2021)
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