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2020 – today
- 2024
[c11]Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho:
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process. AICAS 2024: 85-89
2010 – 2019
- 2019
- [j8]Kai Xu
, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54(7): 2028-2037 (2019) - [c10]Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - 2018
- [j7]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3756-3768 (2018) - 2017
- [j6]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Iman Madadi, Massoud Tohidian, Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski:
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52(4): 1144-1162 (2017) - 2016
- [j5]Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski:
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51(7): 1547-1565 (2016) - [c9]Feng-Wei Kuo, Sandro Binsfeld Ferreira, Masoud Babaie, Huan-Neng Ron Chen, Lan-chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Guanzhong Huang, Iman Madadi, Massoud Tohidian, Robert Bogdan Staszewski:
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits 2016: 1-2 - 2015
- [c8]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski:
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC 2015: 356-359 - 2014
- [c7]YuLi Hsueh, Lan-Chou Cho, Chih-Hsien Shen, Yi-Chien Tsai, Tzu-Chan Chueh, Tao-Yao Chang, Jui-Lin Hsu, Jing-Hong Conan Zhan:
28.2 A 0.29mm2 frequency synthesizer in 40nm CMOS with 0.19psrms jitter and. ISSCC 2014: 472-473 - 2013
- [c6]Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C. P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, Robert Bogdan Staszewski:
A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. ISSCC 2013: 342-343 - 2011
- [j4]Chi-Yao Yu, Ivan Siu-Chuang Lu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, Hsiang-Hui Chang, Wen-Chang Lee, Sheng-Jui Huang, Tzung-Han Wu, Chinq-Shiun Chiu, George Chien:
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. IEEE J. Solid State Circuits 46(12): 3047-3060 (2011) - [c5]Lan-Chou Cho, Hsiang-Hui Chang, Augusto Marques, Albert Yang, Chinq-Shiun Chiu, Guang-Kaai Dehng:
A 1.22/6.7 ppm/°C VCO with frequency-drifting compensator in 60 nm CMOS. A-SSCC 2011: 101-104 - [c4]Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien:
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. ISSCC 2011: 364-366
2000 – 2009
- 2009
- [j3]Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu:
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. IEEE J. Solid State Circuits 44(3): 775-783 (2009) - 2008
- [j2]Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 404-408 (2008) - [c3]Kun-Hung Tsai, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu:
3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. ISSCC 2008: 466-467 - 2007
- [j1]Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. IEEE J. Solid State Circuits 42(6): 1261-1270 (2007) - [c2]Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. ISSCC 2007: 48-586 - 2006
- [c1]Chihun Lee, Lan-chou Cho, Shen-Iuan Liu:
A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. CICC 2006: 397-400
Coauthor Index
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