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ORCIDMark Chen 0001
Person information
- affiliation: Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan
Other persons with the same name
- Mark Chen — disambiguation page
- Mark Chen 0002
![[0000-0001-9369-5830]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-9369-5830")
(aka: Mark I. C. Chen, Mark I-Cheng Chen) — National University of Singapore and National University Health System, Saw Swee Hock School of Public Health, Singapore (and 1 more) - Mark Chen 0003 — OpenAI, San Francisco, CA, USA
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2020 – today
- 2020
[c7]Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen:
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j2]Kai Xu, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54(7): 2028-2037 (2019) - [c6]Feng-Wei Kuo, Zhirui Zong, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - [c5]Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. VLSI Circuits 2019: 164- - 2018
- [j1]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Mark Chen, Robert Bogdan Staszewski:
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3756-3768 (2018) - [c4]Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. VLSI Circuits 2018: 179-180 - 2017
- [c3]Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 0.031mm2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOS. CICC 2017: 1-4 - [c2]Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski:
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. ISSCC 2017: 332-333 - 2016
- [c1]Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski:
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2
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