"A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with ..."

Chen-Ting Ko et al. (2019)

> Home

Details and statistics

DOI: 10.23919/VLSIC.2019.8777946

access: closed

type: Conference or Workshop Paper

metadata version: 2019-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/KoKSCH019
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/KoKSCH019
Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. VLSI Circuits 2019: 164-

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.