"A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital ..."

Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen (1999)

> Home

Details and statistics

DOI: 10.1109/ISCAS.1999.780798

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/WangCC99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/WangCC99
Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) 1999: 528-531

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.