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2010 – 2019
- 2012
[j4]Tsan-Nan Chien, Sung-Huai Hsieh
, Po-Hsun Cheng, Ying-Pei Chen, Sao-Jie Chen, Jer-Junn Luh, Heng-Shuen Chen, Jin-Shin Lai:
Usability Evaluation of Mobile Medical Treatment Carts: Another Explanation by Information Engineers. J. Medical Syst. 36(3): 1327-1334 (2012)
2000 – 2009
- 2009
- [c6]Po-Hsun Cheng, Ying-Pei Chen, Jin-Shin Lai:
An Interflow System Requirement Analysis in Health Informatics Field. CSIE (7) 2009: 712-716 - [c5]Ying-Pei Chen, Tsan-Nan Chien, Po-Hsun Cheng, Sao-Jie Chen:
An Agile and Low Cost FPGA Implementation of MPEG-2 TS Remultiplexer for CATV Head-End Equipment. ISPAN 2009: 722-726 - [c4]Po-Hsun Cheng, Ying-Pei Chen, Mei-Ju Su:
A Web Likely-word Instant Organizer (WebLio) - Dynamic Hints During Knowledge Collectors Move Mouse Over a Sentence. WEBIST 2009: 435-438 - 2003
- [j3]Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen:
An area-saving decoder structure for ROMs. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 581-589 (2003) - 2002
- [j2]Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen:
Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design 14(4): 373-381 (2002) - 2001
- [c3]Chua-Chin Wang, Ya-Hsin Hsueh, Ying-Pei Chen:
An area-saving 3-dimensional decoder structure for ROMs. ICECS 2001: 573-576 - 2000
- [j1]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design 11(2): 107-113 (2000) - [c2]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
Design of an inter-plane circuit for clocked PLAs. ISCAS 2000: 281-284
1990 – 1999
- 1999
- [c1]Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen:
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) 1999: 528-531
Coauthor Index
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