"A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology."

Chua-Chin Wang, Gang-Neng Sung (2006)

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DOI: 10.1109/ISVLSI.2006.5

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Chua-Chin Wang, Gang-Neng Sung:
A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. ISVLSI 2006: 405-410

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