"A 1.0 GHz clock generator design with a negative delay using a single-shot ..."

Chua-Chin Wang, Yih-Long Tseng, Rong-Sui Kao (2001)

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DOI: 10.1109/ICECS.2001.957413

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

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Chua-Chin Wang, Yih-Long Tseng, Rong-Sui Kao:
A 1.0 GHz clock generator design with a negative delay using a single-shot locking method. ICECS 2001: 1123-1126

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