"Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm ..."

Chua-Chin Wang et al. (2020)

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DOI: 10.1109/TVLSI.2020.3008424

access: closed

type: Journal Article

metadata version: 2020-09-19

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Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh:
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2069-2073 (2020)

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