"GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS ..."

Jhih-Ying Ke et al. (2024)

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DOI: 10.1109/AICAS59952.2024.10595891

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-31

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Jhih-Ying Ke, Lean Karlo Santos Tolentino, Cheng-Yao Lo, Tzung-Je Lee, Chua-Chin Wang:
GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process. AICAS 2024: 95-99

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