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ORCIDICICDT 2012: Austin, TX, USA
- IEEE International Conference on IC Design & Technology, ICICDT 2012, Austin, TX, USA, May 30 - June 1, 2012. IEEE 2012, ISBN 978-1-4673-0146-6
- Suming Lai, Peng Li, Zhiyu Zeng:
Design and analysis of IC power delivery with on-chip voltage regulation. 1-4 - Kanak B. Agarwal, Shayak Banerjee:
Design driven patterning optimizations for low K1 lithography. 1-4 - Inhak Han, Youngsoo Shin:
Synthesis of clock gating logic through factored form matching. 1-4 - Donkyu Baek, Insup Shin, Youngsoo Shin:
Gate delay modeling for static timing analysis of body-biased circuits. 1-4 - Xiaoliang Bai, Prayag Patel, Xiaonan Zhang:
A new statistical setup and hold time definition. 1-4 - Ziyuan Liu, Fumihiko Hayashi, Shinji Fujieda, Markus Wilde
, Katsuyuki Fukutani:
Reliability driven guideline for BEOL Optimization: Protecting MOS stacks from hydrogen-related impurity penetration. 1-4 - Jacopo Franco, Ben Kaczer, Jérôme Mitard, Maria Toledano-Luque, Felice Crupi, Geert Eneman, Ph. J. Rousse, Tibor Grasser, M. Cho, Thomas Kauerauf, Liesbeth Witters, Geert Hellings, L.-Å. Ragnarsson, Naoto Horiguchi, Marc M. Heyns, Guido Groeseneken:
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications. 1-4 - Koji Eriguchi, Yoshinori Nakakubo, Asahiko Matsuda, Masayuki Kamei, Yoshinori Takao, Kouichi Ono:
Optimization problems for plasma-induced damage - A concept for plasma-induced damage design. 1-4 - Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. 1-4 - Yuichiro Mitani, Shigeto Fukatsu, Daisuke Hagishima, Kazuya Matsuzawa:
Lifetime prediction of channel hot carrier degradation in pMOSFETs separating NBTI component. 1-4 - Paul Bassett, Martin Saint-Laurent:
Energy efficient design techniques for a digital signal processor. 1-4 - Carolynn Bernier, Jean-Baptiste David:
BAW filters for ultra-low power narrow-band applications. 1-4 - Ayobami B. Iji, Forest Zhu, Michael Heimlich:
Design of low power, wider tuning range CMOS voltage control oscillator for ultra wideband applications. 1-4 - Hung Viet Nguyen, Youngmin Kim:
32 nm FinFET-based 0.7-to-1.1 V digital voltage sensor with 50 mV resolution. 1-4 - Nahla T. Abou-El-Kheir, Moataz S. El-Kharashi, Magdy A. El-Moursy:
A low power programmable FIR filter using sharing multiplication technique. 1-4 - Sih-Yu Chen, Chua-Chin Wang:
Single-ended disturb-free 5T loadless SRAM Cell using 90 nm CMOS process. 1-4 - Chenyun Pan, Azad Naeemi:
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. 1-5 - Ahmet Ceyhan, Azad Naeemi:
System-level design and performance modeling for multilevel interconnect networks for carbon nanotube field-effect transistors. 1-4 - Andrey Y. Serov, Zuanyi Li, Kyle L. Grosse, Albert D. Liao, David Estrada, Myung-Ho Bae, Feng Xiong, William P. King, Eric Pop:
Nanoscale power and heat management in electronics. 1-5 - Chandra Nimmagadda, Durodami Lisk, Riko Radojcic:
3D stacking: Where the rubber meets the road. 1-3 - Thuy Dao, Tania Thomas, David Marx, David Grant:
Evaluation of non-destructive etch depth measurement for through silicon vias. 1-4 - Wei Guo, Geert Van der Plas, Andrej Ivankovic, Geert Eneman, Vladimir Cherman, Bart De Wachter, Abdelkarim Mercha, Mario Gonzalez, Yann Civale, Augusto Redolfi, Thibault Buisson, A. Jourdan, Bart Vandevelde, Kenneth J. Rebibis, Ingrid De Wolf, Antonio La Manna, Gerald Beyer, Eric Beyne, Bart Swinnen:
3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps. 1-4 - Joris Lacord, Perrine Batude, Gérard Ghibaudo, Frédéric Boeuf:
Analytical modeling of parasitics in monolithically integrated 3D inverters. 1-4 - Fabio Pellizzer, Roberto Bez:
"Phase-Change Memories for nano-scale technology and design". 1-4 - Jane Yater, S.-T. Kang, C. M. Hong, B. Min, D. Kolar, K. Loiko, J. Shen, B. Winstead, H. Gasquet, S. Mohammed, A. Hardell, W. Malloch, B. Cook, R. Syzdek, A. Jarrar, J. Feddeler, K. Baker, K. M. Chang, S. Herrin, R. Parks, G. Chindalore:
First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories. 1-3 - Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe:
Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction. 1-4 - Sylvain Clerc, Fady Abouzeid, Gilles Gasiot, David Gauthier, Dimitri Soussan, Philippe Roche:
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance. 1-4 - Gururaj Shamanna, Raja Gaurav, Y. K. Raghavendra, Percy Marfatia, Bhunesh S. Kshatri:
Using ECC and redundancy to minimize vmin induced yield loss in 6T SRAM arrays. 1-4 - Francis Fradette, Eric J. Balster, Frank A. Scarpino, Kerry L. Hill:
Dynamic Stage Element Matching (DSEM) in Pipeline Analog to Digital Converters (ADC). 1-4 - Tzung-Je Lee, Doron Shmilovitz, Yi-Jie Hsieh, Chua-Chin Wang:
Temperature and process compensated clock generator using feedback TPC bias. 1-4 - Soo Youn Kim, Wing-Fai Loke, Sang Phill Park, Byunghoo Jung, Kaushik Roy:
Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications. 1-4 - Andrea Neviani, Andrea Bevilacqua, Andrea Gerosa, Daniele Vogrig:
Low-power ultra-Wide-Band Impulse Radio transceivers for short range communications. 1-4 - Rouhollah Feghhi, Sasan Naseh:
A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixer. 1-4 - Chang Yong Kang, K. W. Ang, R. Hill, W. Y. Loh, Jungwoo Oh, Rinus Lee, David Gilmer, Gennadi Bersuker, C. Hobbs, Paul Kirsch, Klaus Hummler, S. Arkalgud, Raj Jammy:
Emerging CMOS and beyond CMOS technologies for an ultra-low power 3D world. 1-4 - Maud Vinet, T. Hook, Yannick Le Tiec, R. Murphy, Shom Ponoth, Laurent Grenouillet, Romain Wacquez:
Variability in Fully Depleted MOSFETs. 1-3 - Walter Schwarzenbach, N. Daval, S. Kerdiles, G. Chabanne, C. Figuet, S. Guerroudj, O. Bonnin, X. Cauchy, Bich-Yen Nguyen, Christophe Maleville:
Strained silicon on insulator substrates for fully depleted application. 1-4 - D. H. Triyoso, V. Jaschke, Jeff Shu, S. Mutas, Klaus Hempel, Jamie K. Schaeffer, Markus Lenski:
Robust PEALD SiN spacer for gate first high-k metal gate integration. 1-4 - Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta:
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. 1-4 - Balaji Jayaraman, Sneha Gupta, Yanli Zhang, Puneet Goyal, Herbert Ho, Rishikesh Krishnan, Sunfei Fang, Sungjae Lee, Douglas Daley, Kevin McStay, Bernhard Wunder, John Barth, Sadanand Deshpande, Paul C. Parries, Rajeev Malik, Paul D. Agnello, Scott R. Stiffler, Subramanian S. Iyer:
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond. 1-4 - Ku He, Andreas Gerstlauer, Michael Orshansky:
Low-energy signal processing using circuit-level timing-error acceptance. 1-4 - Kishore Kollu, Trey Jackson, Farhad Kharas, Anant Adke:
Unifying design data during verification: Implementing Logic-Driven Layout analysis and debug. 1-5 - Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Emrah Acar, Frank Liu, Rob A. Rutenbar:
Spatial variation decomposition via sparse regression. 1-4 - Chih-Lin Chen, Hsin-Yuan Tseng, Ron-Chi Kuo, Chua-Chin Wang:
On-chip MOS PVT variation monitor for slew rate self-adjusting 2×VDD output buffers. 1-4 - Dimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville:
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. 1-4 - Philippe Galy, Jean Jimenez, Johan Bourgeat, A. Dray, Ghislain Troussier, Boris Heitz, Nicolas Guitard, David Marin-Cudraz, H. Beckrich-Ros:
BIMOS transistor and its applications in ESD protection in advanced CMOS technology. 1-4 - Jean Jimenez, Philippe Galy, Johan Bourgeat, Boris Heitz:
High swing low capacitance ESD RF protections in advanced CMOS technologies. 1-4 - Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
Extending energy-saving voltage scaling in ultra low voltage integrated circuit designs. 1-4 - Chih-Lin Chen, Yi Hu, Wayne Luo, Chua-Chin Wang, Chun-Ying Juan:
A high voltage analog multiplexer with digital calibration for battery management systems. 1-4 - Bao Liu, Lu Wang:
Minimum logic of guaranteed single soft error resilience based on group distance-two code. 1-4
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