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Vita Pi-Ho Hu

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2020 – today

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2024
[c22]
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Hao-Chi Chiu, Vita Pi-Ho Hu:
Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs. ISCAS 2024: 1-5
2023
[c21]
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Vita Pi-Ho Hu:
Energy-Efficient SRAM with Emerging Technologies. ICICDT 2023: xxxv
2021
[c20]
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Vita Pi-Ho Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, Cheng-Yang Weng:
Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node. ISCAS 2021: 1-5
2020
[c19]
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Yen-Wei Lee, Vita Pi-Ho Hu:
Improved Energy Efficiency for Ferroelectric FET Non-Volatile Memory using Split-Gate Design. ISCAS 2020: 1-5

2010 – 2019

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2019
[c18]
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Zhe-An Zheng, Vita Pi-Ho Hu:
Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation. ISCAS 2019: 1-5
[c17]
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Hung-Han Lin, Vita Pi-Ho Hu:
Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET. ISQED 2019: 241-246
2016
[c16]
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Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs. ISCAS 2016: 2106-2109
2015
[c15]
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Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ICICDT 2015: 1-4
[c14]
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells. ISCAS 2015: 601-604
[c13]
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Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ISCAS 2015: 2325-2328
[c12]
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Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. SoCC 2015: 339-344
2014
[j6]
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Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 389-399 (2014)
[j5]
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Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. Microelectron. Reliab. 54(4): 698-711 (2014)
[j4]
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Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3339-3347 (2014)
[c11]
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells. ISCAS 2014: 1122-1125
[c10]
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Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. ISCAS 2014: 1130-1133
[c9]
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Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. ISLPED 2014: 255-258
2013
[c8]
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  - conf/icicdt/YangCFHSC13
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Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Impacts of single trap induced random telegraph noise on Si and Ge nanowire FETs, 6T SRAM cells and logic circuits. ICICDT 2013: 61-64
[c7]
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates. ISQED 2013: 347-352
2012
[j3]
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Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 878-882 (2012)
[j2]
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Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1201-1210 (2012)
[c6]
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Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
A comprehensive comparative analysis of FinFET and Trigate device, SRAM and logic circuits. APCCAS 2012: 463-466
[c5]
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells. ESSDERC 2012: 77-80
[c4]
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Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Ming-Fu Tsai, Chia-Hao Pao, Pin Su, Ching-Te Chuang:
A comparative analysis of tunneling FET circuit switching characteristics and SRAM stability and performance. ESSDERC 2012: 157-160
[c3]
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Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang:
Impacts of random telegraph noise on the analog properties of FinFET and trigate devices and Widlar current source. ICICDT 2012: 1-4
2011
[j1]
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  - journals/esticas/HuFSC11
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 335-342 (2011)
[c2]
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Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Analysis of power-performance for ultra-thin-body GeOI logic circuits. ISLPED 2011: 115-120

2000 – 2009

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2009
[c1]
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Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang:
Design and analysis of ultra-thin-body SOI based subthreshold SRAM. ISLPED 2009: 9-14

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