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2020 – today
- 2024
[j25]Ziwen Li
, Yu Ma, Jindong Zhou, Pingqiang Zhou:
Spiking-NeRF: Spiking Neural Network for Energy-Efficient Neural Rendering. ACM J. Emerg. Technol. Comput. Syst. 20(3): 10:1-10:23 (2024)- [j24]Jinxin Dong, Pingqiang Zhou:
Detecting Adversarial Examples Utilizing Pixel Value Diversity. ACM Trans. Design Autom. Electr. Syst. 29(3): 41:1-41:12 (2024) - [j23]Yankun Zhu, Pingqiang Zhou:
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1919-1929 (2024) - [c39]Hongjian Zhou, Yaguang Li, Xin Xiong, Pingqiang Zhou:
A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs. ASPDAC 2024: 411-416 - [c38]Zhechen Yuan, Binzhe Yuan, Yuhan Gu, Yueyang Zheng, Yunxiang He, Xuexin Wang, Chaolin Rao, Pingqiang Zhou, Jingyi Yu, Xin Lou:
A 0.59μJ/pixel High-throughput Energy-efficient Neural Volume Rendering Accelerator on FPGA. CICC 2024: 1-2 - [c37]Haochuan Wan, Linjie Ma, Antong Li, Pingqiang Zhou, Jingyi Yu, Xin Lou:
ZeroTetris: A Spacial Feature Similarity-based Sparse MLP Engine for Neural Volume Rendering. DAC 2024: 224:1-224:6 - [c36]Yankun Zhu, Siting Liu, Liyu Yang, Pingqiang Zhou:
LDL-SCA: Linearized Deep Learning Side-Channel Attack Targeting Multi-tenant FPGAs✱. ACM Great Lakes Symposium on VLSI 2024: 583-587 - [c35]Xuexin Wang, Yunxiang He, Xiangyu Zhang, Pingqiang Zhou, Xin Lou:
An Efficient Hardware Volume Renderer for Convolutional Neural Radiance Fields. ISCAS 2024: 1-5 - 2023
- [j22]Jindong Zhou, Yuyang Chen, Youliang Jing, Pingqiang Zhou:
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs. Integr. 88: 196-202 (2023) - [j21]Yu Ma, Linfeng Zheng, Pingqiang Zhou:
A Mapping Method Tolerating SAF and Variation for Memristor Crossbar Array Based Neural Network Inference on Edge Devices. ACM J. Emerg. Technol. Comput. Syst. 19(2): 15:1-15:21 (2023) - [j20]Chaolin Rao, Qing Wu, Pingqiang Zhou, Jingyi Yu, Yuyao Zhang, Xin Lou:
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1625-1638 (2023) - [j19]Kangjie Long, Chaolin Rao, Yunxiang He, Zhechen Yuan, Pingqiang Zhou, Jingyi Yu, Xin Lou:
Analysis and Design of Precision-Scalable Computation Array for Efficient Neural Radiance Field Rendering. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4260-4270 (2023) - [j18]Chip-Hong Chang, Pingqiang Zhou, Yuan Cao, Qiang Liu:
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022). IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5009-5010 (2023) - [j17]Huifan Zhang, Youliang Jing, Pingqiang Zhou:
Machine Learning-Based Device Modeling and Performance Optimization for FinFETs. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1585-1589 (2023) - [j16]Yang Li, Pingqiang Zhou:
Fast and Accurate NoC Latency Estimation for Application-Specific Traffics via Machine Learning. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3569-3573 (2023) - [c34]Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou:
A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks. AICAS 2023: 1-5 - [c33]Yuan Li, Pingqiang Zhou:
Full-Chip Voltage Prediction via Graph Attention Based Neural Networks. ASICON 2023: 1-4 - [c32]Yuanchen Qu, Yu Ma, Pingqiang Zhou:
A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators. DATE 2023: 1-6 - [c31]Yankun Zhu, Jindong Zhou, Pingqiang Zhou:
Exploring Remote Power Attacks Targeting Parallel Data Encryption On Multi-Tenant FPGAs. ACM Great Lakes Symposium on VLSI 2023: 57-62 - 2022
- [j15]Yuan Liu, Jinxin Dong, Pingqiang Zhou:
Defending against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit-plane Slicing. ACM J. Emerg. Technol. Comput. Syst. 18(3): 61:1-61:17 (2022) - [j14]Chaolin Rao, Huangjie Yu, Haochuan Wan, Jindong Zhou, Yueyang Zheng, Minye Wu, Yu Ma, Anpei Chen, Binzhe Yuan, Pingqiang Zhou, Xin Lou, Jingyi Yu:
ICARUS: A Specialized Architecture for Neural Radiance Fields Rendering. ACM Trans. Graph. 41(6): 234:1-234:14 (2022) - [c30]Chaolin Rao, Haochuan Wan, Yueyang Zheng, Pingqiang Zhou, Xin Lou:
An Energy Efficient Precision Scalable Computation Array for Neural Radiance Field Accelerator. APCCAS 2022: 260-264 - [c29]Haochuan Wan, Chaolin Rao, Yueyang Zheng, Pingqiang Zhou, Xin Lou:
SME: A Systolic Multiply-accumulate Engine for MLP-based Neural Network. APCCAS 2022: 270-274 - [c28]Chengrui Zhang, Yu Ma, Pingqiang Zhou:
Thermal-Aware Layout Optimization and Mapping Methods for Resistive Neuromorphic Engines. ASP-DAC 2022: 50-55 - [c27]Yuanchen Qu, Lu Wang, Qingfu Xu, Pingqiang Zhou:
Two-Stage Energy Efficiency Optimization of Switched-Capacitor Converters for IoT Systems. ISCAS 2022: 3068-3072 - [c26]Yueyang Zheng, Chaolin Rao, Haochuan Wan, Yuliang Zhou, Pingqiang Zhou, Jingyi Yu, Xin Lou:
An RRAM-based Neural Radiance Field Processor. SOCC 2022: 1-5 - [i2]Chaolin Rao, Huangjie Yu, Haochuan Wan, Jindong Zhou, Yueyang Zheng, Yu Ma, Anpei Chen, Minye Wu, Binzhe Yuan, Pingqiang Zhou, Xin Lou, Jingyi Yu:
ICARUS: A Lightweight Neural Plenoptic Rendering Architecture. CoRR abs/2203.01414 (2022) - 2021
- [c25]Yu Ma, Chengrui Zhang, Pingqiang Zhou:
Efficient Techniques for Extending Service Time for Memristor-based Neural Networks. APCCAS 2021: 81-84 - [c24]Jinxin Dong, Pingqiang Zhou:
Detecting Adversarial Examples Utilizing Pixel Value Diversity. AsianHOST 2021: 1-6 - [c23]Chenguang Zhang, Pingqiang Zhou:
A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators. ASP-DAC 2021: 43-48 - [c22]Yu Ma, Pingqiang Zhou:
Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime. ASP-DAC 2021: 390-395 - [c21]Yu Ma, Linfeng Zheng, Pingqiang Zhou:
Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping. ACM Great Lakes Symposium on VLSI 2021: 313-318 - 2020
- [j13]Leilei Wang, Lu Wang, Cheng Zhuo, Pingqiang Zhou:
Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip. IEEE Access 8: 85900-85911 (2020) - [j12]Yajun Yang, Zhang Chen, Yuan Liu, Tsung-Yi Ho, Yier Jin, Pingqiang Zhou:
How Secure Is Split Manufacturing in Preventing Hardware Trojan? ACM Trans. Design Autom. Electr. Syst. 25(2): 20:1-20:23 (2020) - [c20]Yuan Liu, Pingqiang Zhou:
Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing. AsianHOST 2020: 1-4 - [i1]Yani Feng, Kejun Tang, Lianxing He, Pingqiang Zhou, Qifeng Liao:
Tensor Train Random Projection. CoRR abs/2010.10797 (2020)
2010 – 2019
- 2019
- [j11]Wei Gao, Pingqiang Zhou:
Customized High Performance and Energy Efficient Communication Networks for AI Chips. IEEE Access 7: 69434-69446 (2019) - [j10]Leilei Wang, Cheng Zhuo, Pingqiang Zhou:
Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips. Integr. 65: 322-330 (2019) - [j9]Xiangwei Cai, Jieming Yin, Pingqiang Zhou:
An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems. Integr. 65: 344-350 (2019) - [j8]Wei Gao, Zhiliang Qian, Pingqiang Zhou:
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation. Integr. 65: 351-361 (2019) - [j7]Yaguang Li, Cheng Zhuo, Pingqiang Zhou:
A Cross-Layer Framework for Temporal Power and Supply Noise Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1914-1927 (2019) - [j6]Yang Liu, Xiaoming Chen, Dileep Kadambi, Ajinkya Bari, Xin Li, Shiyan Hu, Pingqiang Zhou:
Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems. ACM Trans. Cyber Phys. Syst. 3(1): 5:1-5:17 (2019) - [c19]Yu Ma, Dingcheng Jia, Wei Gao, Pingqiang Zhou:
Addressing Aging Issues in Heterogeneous Three-Dimensional Integrated Circuits. ASICON 2019: 1-4 - [c18]Yu Ma, Dingcheng Jia, Huifan Zhang, Ruoyu Wang, Pingqiang Zhou:
A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays. ASICON 2019: 1-4 - [c17]Yu Ma, Linfeng Zheng, Pingqiang Zhou:
CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM. ASICON 2019: 1-4 - [c16]Lu Wang, Leilei Wang, Dejia Shang, Cheng Zhuo, Pingqiang Zhou:
Optimizing the Energy Efficiency of Power Supply in Heterogeneous Multicore Chips with Integrated Switched-Capacitor Converters. DATE 2019: 836-841 - 2018
- [c15]Jiuxin Zhang, Pingqiang Zhou:
Integrating low-resolution surveillance camera and smartphone inertial sensors for indoor positioning. PLANS 2018: 410-416 - 2017
- [j5]Xiaochen Liu, Shupeng Sun, Xin Li, Haifeng Qian, Pingqiang Zhou:
Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 421-434 (2017) - [c14]Yaguang Li, Pingqiang Zhou:
An outlier detection method and its application to multicore-chip power estimation. ASICON 2017: 460-463 - 2016
- [c13]Zhang Chen, Pingqiang Zhou, Tsung-Yi Ho, Yier Jin:
How secure is split manufacturing in preventing hardware trojan? AsianHOST 2016: 1-6 - 2015
- [c12]Xiaochen Liu, Shupeng Sun, Pingqiang Zhou, Xin Li, Haifeng Qian:
A statistical methodology for noise sensor placement and full-chip voltage map generation. DAC 2015: 94:1-94:6 - 2014
- [j4]Pingqiang Zhou, Ayan Paul, Chris H. Kim, Sachin S. Sapatnekar:
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 22(9): 1954-1967 (2014) - [c11]Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, Antonia Zhai:
Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems. IPDPS 2014: 293-303 - 2013
- [c10]Pingqiang Zhou, Vivek Mishra, Sachin S. Sapatnekar:
Placement optimization of power supply pads based on locality. DATE 2013: 1655-1660 - 2012
- [j3]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar:
Optimized 3D Network-on-Chip Design Using Simulated Allocation. ACM Trans. Design Autom. Electr. Syst. 17(2): 12:1-12:19 (2012) - [c9]Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar:
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD 2012: 243-246 - [c8]Pingqiang Zhou, Won Ho Choi, Bongjin Kim, Chris H. Kim, Sachin S. Sapatnekar:
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications. ICCAD 2012: 263-270 - [c7]Jieming Yin, Pingqiang Zhou, Anup Holey, Sachin S. Sapatnekar, Antonia Zhai:
Energy-efficient non-minimal path on-chip interconnection network for heterogeneous systems. ISLPED 2012: 57-62 - 2011
- [c6]Pingqiang Zhou, Dong Jiao, Chris H. Kim, Sachin S. Sapatnekar:
Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network. CICC 2011: 1-4 - [c5]Pingqiang Zhou, Jieming Yin, Antonia Zhai, Sachin S. Sapatnekar:
NoC frequency scaling with flexible-pipeline routers. ISLPED 2011: 403-408 - 2010
- [j2]Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong:
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19(7): 1483-1495 (2010) - [c4]Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar:
Application-specific 3D Network-on-Chip design using simulated allocation. ASP-DAC 2010: 517-522
2000 – 2009
- 2009
- [j1]Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity. IEEE Des. Test Comput. 26(5): 15-25 (2009) - [c3]Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors. ASP-DAC 2009: 179-184 - 2007
- [c2]Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong:
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics 2007: 338-343 - [c1]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597
Coauthor Index
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