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ORCID61st DAC 2024: San Francisco, CA, USA
- Vivek De:
Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM 2024, ISBN 979-8-4007-0601-1 - Junyao Wang
, Mohammad Abdullah Al Faruque:
SMORE: Similarity-Based Hyperdimensional Domain Adaptation for Multi-Sensor Time Series Classification. 1:1-1:6 - Yifan Zhu, Peinan Li, Yunkai Bai, Yubiao Huang, Shiwen Wang, Xingbin Wang, Dan Meng, Rui Hou:
EnTurbo: Accelerate Confidential Serverless Computing via Parallelizing Enclave Startup Procedure. 2:1-2:6 - Yunkai Bai, Peinan Li, Yubiao Huang, Shiwen Wang, Xingbin Wang, Dan Meng, Rui Hou:
SecPaging: Secure Enclave Paging with Hardware-Enforced Protection against Controlled-Channel Attacks. 3:1-3:6 - Runzhen Xue, Mingyu Yan, Dengke Han, Yihan Teng, Zhimin Tang, Xiaochun Ye, Dongrui Fan:
GDR-HGNN: A Heterogeneous Graph Neural Networks Accelerator Frontend with Graph Decoupling and Recoupling. 4:1-4:6 - Yan Wang, Xingbin Wang, Zechao Lin, Yulan Su, Sisi Zhang, Rui Hou, Dan Meng:
Garrison: A High-Performance GPU-Accelerated Inference System for Adversarial Ensemble Defense. 5:1-5:6 - Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. 6:1-6:6 - Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang:
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. 7:1-7:6 - Ali Hajiabadi, Archit Agarwal, Andreas Diavastos, Trevor E. Carlson:
Levioso: Efficient Compiler-Informed Secure Speculation. 8:1-8:6 - Ali Hajiabadi, Trevor E. Carlson:
Conjuring: Leaking Control Flow via Speculative Fetch Attacks. 9:1-9:6 - Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, Haomin Li, Shiyuan Huang, Zhuoran Song, Songwen Pei, Li Jiang:
INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding. 10:1-10:6 - Che Chang, Tsung-Wei Huang, Dian-Lun Lin, Guannan Guo, Shiju Lin:
Ink: Efficient Incremental k-Critical Path Generation. 11:1-11:6 - Chenyu Wang, Zhen Dong, Daquan Zhou, Zhenhua Zhu, Yu Wang, Jiashi Feng, Kurt Keutzer:
EPIM: Efficient Processing-In-Memory Accelerators based on Epitome. 12:1-12:6 - Tuo Dai, Bizhao Shi, Guojie Luo:
G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning. 13:1-13:6 - Bizhao Shi, Tuo Dai, Jiaxi Zhang, Xuechao Wei, Guojie Luo:
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. 14:1-14:6 - Sunghye Park, Dohun Kim, Seokhyeong Kang:
HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication. 15:1-15:6 - Zhuo Su, Zehong Yu, Dongyan Wang, Rui Wang, Yang Tao, Yu Jiang:
CFTCG: Test Case Generation for Simulink Model through Code Based Fuzzing. 16:1-16:6 - Jiarui Wang, Xun Jiang, Yibo Lin:
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. 17:1-17:6 - Tian-Fu Chen, Jie-Hong Roland Jiang:
Boolean Matching Reversible Circuits: Algorithm and Complexity. 18:1-18:6 - Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin:
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs. 19:1-19:6 - Zehong Yu, Zhuo Su, Yu Jiang, Aiguo Cui, Rui Wang:
Efficient Code Generation for Data-Intensive Simulink Models via Redundancy Elimination. 20:1-20:6 - Yifan Cheng, Zehong Yu, Zhuo Su, Ting Chen, Xiaosong Zhang, Yu Jiang:
AccMoS: Accelerating Model Simulation for Simulink via Code Generation. 21:1-21:6 - Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin:
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. 22:1-22:6 - Hiroshi Sawada, Kazuo Aoyama, Kohei Ikeda:
Zeroth-Order Optimization of Optical Neural Networks with Linear Combination Natural Gradient and Calibrated Model. 23:1-23:6 - Yansong Xu, Dongxu Lyu, Zhenyu Li, Yuzhou Chen, Zilong Wang, Gang Wang, Zhican Wang, Haomin Li, Guanghui He:
DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing. 24:1-24:6 - Hashan Roshantha Mendis, Chih-Kai Kang, Chun-Han Lin, Ming-Syan Chen, Pi-Cheng Hsiu:
Deep Reorganization: Retaining Residuals in TinyML. 25:1-25:6 - Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li:
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. 26:1-26:6 - Chengning Wang, Dan Feng, Yuchong Hu, Wei Tong, Jingning Liu:
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM. 27:1-27:6 - Xin Zhang, Zhi Zhang, Qingni Shen, Wenhao Wang, Yansong Gao, Zhuoxi Yang, Zhonghai Wu:
ThermalScope: A Practical Interrupt Side Channel Attack Based on Thermal Event Interrupts. 28:1-28:6 - Ruiyang Qin, Jun Xia, Zhenge Jia, Meng Jiang, Ahmed Abbasi, Peipei Zhou, Jingtong Hu, Yiyu Shi:
Enabling On-Device Large Language Model Personalization with Self-Supervised Data Selection and Synthesis. 29:1-29:6 - Sven Thijssen, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions. 30:1-30:6 - Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun:
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. 31:1-31:6 - Wang Fang, Mingsheng Ying:
SymPhase: Phase Symbolization for Fast Simulation of Stabilizer Circuits. 32:1-32:6 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Dominic Simon, Sumit Jha, Rickard Ewetz:
Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation. 33:1-33:6 - Weikai Xu, Jin Luo, Qianqian Huang, Ru Huang:
Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator. 34:1-34:6 - Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin:
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. 35:1-35:6 - Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. 36:1-36:6 - Xin Zhao, Zhicheng Hu, Zilong Guo, Haodong Fan, Xi Yang, Jing Zhou, Liang Chang:
A RRAM-based High Energy-efficient Accelerator Supporting Multimodal Tasks for Virtual Reality Wearable Devices. 37:1-37:6 - HoSun Choi, Chanho Park, Euijun Kim, William J. Song:
Nona: Accurate Power Prediction Model Using Neural Networks. 38:1-38:6 - Zihao Chen, Jiangli Huang, Yiting Liu, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng:
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. 39:1-39:6 - Anastasis Vagenas, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis:
Advanced gate-level glitch modeling using ANNs. 40:1-40:6 - Sunan Zou, Guojie Luo:
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation. 41:1-41:6 - Xueyuan Liu, Zhuoran Song, Hao Chen, Xing Li, Xiaoyao Liang:
MoC: A Morton-Code-Based Fine-Grained Quantization for Accelerating Point Cloud Neural Networks. 42:1-42:6 - Haishuang Fan, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse. 43:1-43:6 - Ranyang Zhou, Sabbir Ahmed, Adnan Siraj Rakin, Shaahin Angizi:
DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs. 44:1-44:6 - Tianyu Guo, Xuanteng Huang, Kan Wu, Xianwei Zhang, Nong Xiao:
SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism. 45:1-45:6 - Junzhuo Zhou, Li Huang, Haoxuan Xia, Yihui Cai, Leilei Jin, Xiao Shi, Wei W. Xing, Ting-Jung Lin, Lei He:
LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning. 46:1-46:6 - Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang:
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. 47:1-47:6 - Ning Lin, Shaocong Wang, Yue Zhang, Yangu He, Kwunhang Wong, Arindam Basu, Dashan Shang, Xiaoming Chen, Zhongrui Wang:
Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of DNNs. 48:1-48:6 - Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo:
Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. 49:1-49:6 - Kevin Mato, Stefan Hillmich, Robert Wille:
Mixed-Dimensional Qudit State Preparation Using Edge-Weighted Decision Diagrams. 50:1-50:6 - Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler:
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. 51:1-51:6 - Nguyen-Dong Ho, Gyujun Jeong, Cheol-Min Kang, Seungkyu Choi, Ik-Joon Chang:
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy. 52:1-52:6 - Yunda Tsai, Mingjie Liu, Haoxing Ren:
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model. 53:1-53:6 - Cheng Chu, Zhenxiao Fu, Yilun Xu, Gang Huang, Hausi A. Müller, Fan Chen, Lei Jiang:
TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer. 54:1-54:6 - Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Duet: A Collaborative User Driven Recommendation System for Edge Devices. 55:1-55:6 - Tianqi Zhang, Neha Prakriya, Sumukh Pinge, Jason Cong, Tajana Rosing:
SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering. 56:1-56:6 - Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li:
IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. 57:1-57:6 - Ning Yang, Fangxin Liu, Zongwu Wang, Haomin Li, Zhuoran Song, Songwen Pei, Li Jiang:
EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks. 58:1-58:6 - Jinhyo Jung, Hwisoo So, Woobin Ko, Sumedh Shridhar Joshi, Yebon Kim, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee:
Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs. 59:1-59:6 - Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. 60:1-60:6 - Yi Wang, Huan Liu, Jianan Yuan, Jiaxian Chen, Tianyu Wang, Chenlin Ma, Rui Mao:
Leanor: A Learning-Based Accelerator for Efficient Approximate Nearest Neighbor Search via Reduced Memory Access. 61:1-61:6 - Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. 62:1-62:6 - Yucong Huang, Jingyu He, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui, Terry Tao Ye:
RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing. 63:1-63:6 - Qingjie Zhang, Lijun Chi, Di Wang, Mounira Msahli, Gérard Memmi, Tianwei Zhang, Chao Zhang, Han Qiu:
Laser Shield: a Physical Defense with Polarizer against Laser Attacks on Autonomous Driving Systems. 65:1-65:6 - Pengcheng Qiu, Guiming Wu, Tingqiang Chu, Changzheng Wei, Runzhou Luo, Ying Yan, Wei Wang, Hui Zhang:
MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof. 66:1-66:6 - Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He:
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption. 67:1-67:6 - Zhuoran Song, Chunyu Qi, Yuanzheng Yao, Peng Zhou, Yanyi Zi, Nan Wang, Xiaoyao Liang:
TSAcc: An Efficient \underline{T}empo-\underline{S}patial Similarity Aware \underline{Acc}elerator for Attention Acceleration. 68:1-68:6 - Yinan Xu, Sa Wang, Dan Tang, Ninghui Sun, Yungang Bao:
PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs. 69:1-69:6 - Hanrui Zhao, Niuniu Qi, Mengxin Ren, Xia Zeng, Zhenbing Zeng, Zhengfeng Yang:
Neural Barrier Certificates Synthesis of NN-Controlled Continuous Systems via Counterexample-Guided Learning. 70:1-70:6 - Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. 71:1-71:6 - Jaekyung Im, Seokhyeong Kang:
SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation. 72:1-72:6 - Nils Bosbach, Niko Zurstraßen, Rebecca Pelke, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. 73:1-73:6 - Weijie Fang, Longkun Guo, Jiawei Lin, Silu Xiong, Huan He, Jiacen Xu, Jianli Chen:
Obstacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Circuit Board. 74:1-74:6 - Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann:
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. 74:1-74:6 - Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. 75:1-75:6 - Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan-Luan Lee, Chih-Chun Chang, Donghao Fang, Tsung-Wei Huang:
G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis. 76:1-76:6 - Baharealsadat Parchamdar, Benjamin Carrión Schäfer:
Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue. 77:1-77:6 - Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu:
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. 78:1-78:6 - Eunji Kwon, Minxuan Zhou, Weihong Xu, Tajana Rosing, Seokhyeong Kang:
RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers. 79:1-79:6 - Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli:
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. 80:1-80:6 - Md. Abdullah-Al Kaiser, Gourav Datta, Peter A. Beerel, Akhilesh R. Jaiswal:
Toward High-Accuracy, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ. 81:1-81:6 - Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li:
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. 82:1-82:6 - Meng Liu, Shuai Li, Fei Xiao, Ruijie Wang, Chunxue Liu, Liang Wang:
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm. 83:1-83:6 - Chentao Jia, Ming Hu, Zekai Chen, Yanxin Yang, Xiaofei Xie, Yang Liu, Mingsong Chen:
AdaptiveFL: Adaptive Heterogeneous Federated Learning for Resource-Constrained AIoT Systems. 84:1-84:6 - Ying-Jie Jiang, Shao-Yun Fang:
Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization. 85:1-85:6 - Zhiyu An, Xianzhong Ding, Wan Du:
Go Beyond Black-box Policies: Rethinking the Design of Learning Agent for Interpretable and Verifiable HVAC Control. 86:1-86:6 - Zixiao Wang, Yunheng Shen, Xufeng Yao, Wenqian Zhao, Yang Bai, Farzan Farnia, Bei Yu:
ChatPattern: Layout Pattern Customization via Natural Language. 87:1-87:6 - Ruisi Zhang, Farinaz Koushanfar:
EmMark: Robust Watermarks for IP Protection of Embedded Quantized Large Language Models. 88:1-88:6 - Ruoyan Ma, Shengan Zheng, Guifeng Wang, Jin Pu, Yifan Hua, Wentao Wang, Linpeng Huang:
Accelerating Regular Path Queries over Graph Database with Processing-in-Memory. 89:1-89:6 - Kaihong Huang, Dian Shen, Zhaoyang Wang, Juntao Yang, Beilun Wang:
Hynify: A High-throughput and Unified Accelerator for Multi-Mode Nonparametric Statistics. 90:1-90:6 - Hanyu Zhang, Liqiang Lu, Siwei Tan, Size Zheng, Jia Yu, Jianwei Yin:
SpREM: Exploiting Hamming Sparsity for Fast Quantum Readout Error Mitigation. 91:1-91:6 - Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. 92:1-92:6 - Zhenyu Bai, Pranav Dangi, Huize Li, Tulika Mitra:
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs. 93:1-93:6 - Changxu Liu, Hao Zhou, Lan Yang, Jiamin Xu, Patrick Dai, Fan Yang:
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture. 94:1-94:6 - Yuan Zhang, Kuncai Zhong, Jiliang Zhang:
DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency. 95:1-95:6 - Hongyi Wang, Kai Zhong, Haoyu Zhang, Shulin Zeng, Zhenhua Zhu, Xinhao Yang, Shuang Wang, Guohao Dai, Huazhong Yang, Yu Wang:
DySpMM: From Fix to Dynamic for Sparse Matrix-Matrix Multiplication Accelerators. 96:1-96:6 - Hyungjoon Bae, Da Won Kim, Wanyeong Jung:
VVIP: Versatile Vertical Indexing Processor for Edge Computing. 97:1-97:6 - Haoyu Wang, Basel Halak, Jianjie Ren, Ahmad Atamli:
DL2Fence: Integrating Deep Learning and Frame Fusion for Enhanced Detection and Localization of Refined Denial-of-Service in Large-Scale NoCs. 98:1-98:6 - Xuhang Wang, Zhuoran Song, Xiaoyao Liang:
InterArch: Video Transformer Acceleration via Inter-Feature Deduplication with Cube-based Dataflow. 99:1-99:6 - Weiwen Jiang, Youzuo Lin:
QuGeo: An End-to-end Quantum Learning Framework for Geoscience - A Case Study on Full-Waveform Inversion. 100:1-100:6 - Omar Ragheb, Jason Helge Anderson:
CLUMAP: Clustered Mapper for CGRAs with Predication. 101:1-101:6 - Renze Chen, Zijian Ding, Size Zheng, Meng Li, Yun Liang:
MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices. 102:1-102:6 - Christopher Talbot, Deepali Garg, Lawrence T. Pileggi, Kenneth Mai:
An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. 103:1-103:6 - Shize Che, Seongwoo Oh, Haoyun Qin, Yuhao Liu, Anthony Sigillito, Gushu Li:
Fast Virtual Gate Extraction For Silicon Quantum Dot Devices. 104:1-104:6 - Wan Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu:
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner. 105:1-105:6 - Hanqiu Chen, Yitu Wang, Luis Vitório Cargnini, Mohammadreza Soltaniyeh, Dongyang Li, Gongjin Sun, Pradeep Subedi, Andrew Chang, Yiran Chen, Cong Hao:
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model. 106:1-106:6 - Ziyi Guan, Hantao Huang, Yupeng Su, Hong Huang, Ngai Wong, Hao Yu:
APTQ: Attention-aware Post-Training Mixed-Precision Quantization for Large Language Models. 107:1-107:6 - Mate Soos, Kuldeep S. Meel:
Engineering an Efficient Preprocessor for Model Counting. 108:1-108:6 - Hui Yu, Yu Zhang, Ligang He, Donghao He, Qikun Li, Jin Zhao, Xiaofei Liao, Hai Jin, Lin Gu, Haikun Liu:
CDA-GNN: A Chain-driven Accelerator for Efficient Asynchronous Graph Neural Network. 109:1-109:6 - Chuanyu Xue, Tianyu Zhang, Song Han:
Towards Cost-Effective Real-Time High-Throughput End Station Design for Time-Sensitive Networking (TSN). 110:1-110:6 - Hui Yu, Yu Zhang, Andong Tan, Chenze Lu, Jin Zhao, Xiaofei Liao, Hai Jin, Haikun Liu:
RTGA: A Redundancy-free Accelerator for High-Performance Temporal Graph Neural Network Inference. 111:1-111:6 - Zahra Aref, Rohit Suvarna, Bill Hughes, Sandeep Srinivasan, Narayan B. Mandayam:
Advanced Reinforcement Learning Algorithms to Optimize Design Verification. 112:1-112:6 - Shunxiang Lan, Min Tang, Liang Chen, Junfa Mao:
Thermal Resistance Network Derivative (TREND) Model for Efficient Thermal Simulation and Design of ICs and Packages. 113:1-113:6 - Yanghee Lee, Jiwon Lee, Jaewon Kwon, Yongju Lee, Won Woo Ro:
Geneva: A Dynamic Confluence of Speculative Execution and In-Order Commitment Windows. 114:1-114:6 - Mehrdad Morsali, Brendan Reidy, Deniz Najafi, Sepehr Tabrizchi, Mohsen Imani, Mahdi Nikdast, Arman Roohi, Ramtin Zand, Shaahin Angizi:
Lightator: An Optical Near-Sensor Accelerator with Compressive Acquisition Enabling Versatile Image Processing. 115:1-115:6 - Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu:
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. 116:1-116:6 - Jianzhong Liu, Yuheng Shen, Yiru Xu, Hao Sun, Heyuan Shi, Yu Jiang:
Effectively Sanitizing Embedded Operating Systems. 117:1-117:6 - Junze Yu, Zhengxiong Luo, Fangshangyuan Xia, Yanyang Zhao, Heyuan Shi, Yu Jiang:
SPFuzz: Stateful Path based Parallel Fuzzing for Protocols in Autonomous Vehicles. 118:1-118:6 - Jiaxi Jiang, Lancheng Zou, Wenqian Zhao, Zhuolun He, Tinghuan Chen, Bei Yu:
PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry. 119:1-119:6 - Zhuohui Duan, Zelin Yu, Haikun Liu, Xiaofei Liao, Hai Jin, Shijie Zheng, Sihan Wu:
TIGA: Towards Efficient Near Data Processing in SmartNICs-based Disaggregated Memory Systems. 120:1-120:6 - Yuyang Chen, Yiwen Wu, Jingya Wang, Tao Wu, Xuming He, Jingyi Yu, Hao Geng:
LLM-HD: Layout Language Model for Hotspot Detection with GDS Semantic Encoding. 121:1-121:6 - Zhiding Liang, Zhixin Song, Jinglei Cheng, Hang Ren, Tianyi Hao, Rui Yang, Yiyu Shi, Tongyang Li:
Combining Parameterized Pulses and Contextual Subspace for More Practical VQE. 122:1-122:6 - Younghoon Byun, Youngjoo Lee:
Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access. 123:1-123:6 - Chen Chen, Guangyu Hu, Dongsheng Zuo, Cunxi Yu, Yuzhe Ma, Hongce Zhang:
E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis. 124:1-124:6 - Yu Wang, Zibin Sun, You Zhou, Tao Lu, Changsheng Xie, Fei Wu:
Balloon-ZNS: Constructing High-Capacity and Low-Cost ZNS SSDs with Built-in Compression. 125:1-125:6 - Suwan Kim, Taewhan Kim:
Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology. 126:1-126:6 - Nanjiang Qu, Cong Tian, Zhenhua Duan:
DACPara: A Divide-and-Conquer Parallel Approach for High-Quality Logic Rewriting in Large-Scale Circuits. 127:1-127:6 - Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Weichen Liu:
Double-Win NAS: Towards Deep-to-Shallow Transformable Neural Architecture Search for Intelligent Embedded Systems. 128:1-128:6 - Jiapei Zheng, Lizhou Wu, Yutong Su, Jingyi Wang, Zhangcheng Huang, Chixiao Chen, Qi Liu:
CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. 129:1-129:6 - Lin Chen, Qi Xu, Hu Ding:
OTPlace-Vias: A Novel Optimal Transport Based Method for High Density Vias Placement in 3D Circuits. 130:1-130:6 - Hongduo Liu, Peng Xu, Yuan Pu, Lihao Yin, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu:
NeuroSelect: Learning to Select Clauses in SAT Solvers. 131:1-131:6 - Chanwoo Park, Junghwan Park, Premkumar Vincent, Hyunbo Cho:
Accelerating DTCO with a Sample-Efficient Active Learning Framework for TCAD Device Modeling. 132:1-132:6 - Xinyun Zhang, Binwu Zhu, Fangzhou Liu, Ziyi Wang, Peng Xu, Hong Xu, Bei Yu:
Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes. 133:1-133:6 - Xinyun Zhang, Su Zheng, Guojin Chen, Binwu Zhu, Hong Xu, Bei Yu:
Fracturing-aware Curvilinear ILT via Circular E-beam Mask Writer. 134:1-134:6 - Peng Xu, Guojin Chen, Keren Zhu, Tinghuan Chen, Tsung-Yi Ho, Bei Yu:
Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. 135:1-135:6 - Tingting Zhang, Hongqiao Zhang, Zhengkun Yu, Siting Liu, Jie Han:
A High-Performance Stochastic Simulated Bifurcation Ising Machine. 136:1-136:6 - Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia:
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. 137:1-137:6 - Donger Luo, Qi Sun, Xinheng Li, Chen Bai, Bei Yu, Hao Geng:
Knowing The Spec to Explore The Design via Transformed Bayesian Optimization. 138:1-138:6 - Yan-Jen Chen, Cheng-Hsiu Hsieh, Po-Han Su, Shao-Hsiang Chen, Yao-Wen Chang:
Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. 139:1-139:6 - Lian Liu, Zhaohui Xu, Yintao He, Ying Wang, Huawei Li, Xiaowei Li, Yinhe Han:
Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration. 140:1-140:6 - Je-Wei Chuang, Zong-Han Wu, Bo-Ying Huang, Yao-Wen Chang:
Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures. 141:1-141:6 - Guojin Chen, Hongquan He, Peng Xu, Hao Geng, Bei Yu:
Efficient Bilevel Source Mask Optimization. 142:1-142:6 - Zhe Jiang, Shuai Zhao, Ran Wei, Yiyang Gao, Jing Li:
A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips. 143:1-143:6 - Bo Liu, Qingwen Wei, Yang Zhang, Xingyu Xu, Zihan Zou, Xinxiang Huang, Xin Si, Hao Cai:
FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. 144:1-144:6 - Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye:
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. 145:1-145:6 - Chenqi Lin, Tianshi Xu, Zebin Yang, Runsheng Wang, Ru Huang, Meng Li:
FastQuery: Communication-efficient Embedding Table Query for Private LLMs inference. 146:1-146:6 - Abhishek Moitra, Abhiroop Bhattacharjee, Priyadarshini Panda:
PIVOT- Input-aware Path Selection for Energy-efficient ViT Inference. 147:1-147:6 - Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
EMOGen: Enhancing Mask Optimization via Pattern Generation. 148:1-148:6 - Jiechen Huang, Wenjian Yu:
Enhancing 3-D Random Walk Capacitance Solver with Analytic Surface Green's Functions of Transition Cubes. 149:1-149:6 - Chun-Feng Wu, Yuan-Hao Chang, Ming-Chang Yang, Tei-Wei Kuo:
How to Steal CPU Idle Time When Synchronous I/O Mode Becomes Promising. 150:1-150:6 - Zhaohui Chen, Ling Liang, Qi Liu, Zhirui Li, Fahong Zhang, Yanheng Lu, Zhen Gu:
A High-Throughput Private Inference Engine Based on 3D Stacked Memory. 151:1-151:6 - Jennifer Volk, Panagiotis Papanikolaou, Georgios Zervakis, Georgios Tzimpragos:
Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic. 152:1-152:6 - Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, Yuzhe Ma:
CAMO: Correlation-Aware Mask Optimization with Modulated Reinforcement Learning. 153:1-153:6 - Xingyu Meng, Amisha Srivastava, Ayush Arunachalam, Avik Ray, Pedro Henrique Silva, Rafail Psiakis, Yiorgos Makris, Kanad Basu:
NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance. 154:1-154:6 - Filippo Carloni, Davide Conficconi, Marco D. Santambrogio:
ALVEARE: a Domain-Specific Framework for Regular Expressions. 155:1-155:6 - Weidong Cao, Jian Gao, Xin Xin, Xuan Zhang:
Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition. 156:1-156:6 - Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
Massively Parallel AIG Resubstitution. 157:1-157:6 - Zhaojun Lu, Weizong Yu, Peng Xu, Wei Wang, Jiliang Zhang, Dengguo Feng:
An NTT/INTT Accelerator with Ultra-High Throughput and Area Efficiency for FHE. 158:1-158:6 - Jooyeon Jeong, Taewhan Kim:
Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. 159:1-159:6 - Zihan Xia, Jinwook Kim, Mingu Kang:
LEAF: An Adaptation Framework against Noisy Data on Edge through Ultra Low-Cost Training. 160:1-160:6 - Wei W. Xing, Weijian Fan, Zhuohua Liu, Yuan Yao, Yuanqi Hu:
KATO: Knowledge Alignment And Transfer for Transistor Sizing Of Different Design and Technology. 161:1-161:6 - Chaoqun Shen, Gang Qu, Jiliang Zhang:
SPECRUN: The Danger of Speculative Runahead Execution in Processors. 162:1-162:6 - Sukmin Kang, Seongtae Lee, Hyunwoo Koo, Hoon Sung Chwa, Jinkyu Lee:
RT-MDM: Real-Time Scheduling Framework for Multi-DNN on MCU Using External Memory. 163:1-163:6 - Minkyu Lee, Sang-Seol Lee, Kyungho Kim, Eunchong Lee, Sung-Joon Jang:
HAIL-DIMM: Host Access Interleaved with Near-Data Processing on DIMM-based Memory System. 164:1-164:6 - Xiong Xiao, Mingxing Duan, Yingjie Song, Zhuo Tang, Wenjing Yang:
Fake Node-Based Perception Poisoning Attacks against Federated Object Detection Learning in Mobile Computing Networks. 165:1-165:6 - Wei W. Xing, Yanfang Liu, Weijian Fan, Lei He:
Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield Evaluation. 166:1-166:6 - Shuo Xu, Wei Zhang, Mengying Zhao, Zimeng Zhou, Lei Ju:
Cache-aware Task Decomposition for Efficient Intermittent Computing Systems. 167:1-167:6 - Jihe Wang, Ying Wu, Danghui Wang:
SC-GNN: A Communication-Efficient Semantic Compression for Distributed Training of GNNs. 168:1-168:6 - Edward Andert, Francis Mendoza, Hans Walter Behrens, Aviral Shrivastava:
Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring. 169:1-169:6 - Zelin Du, Shaoqi Li, Zixuan Huang, Jin Xue, Kecheng Huang, Tianyu Wang, Zili Shao:
PipeSSD: A Lock-free Pipelined SSD Firmware Design for Multi-core Architecture. 170:1-170:6 - Seongyoung Kang, Sang-Woo Jun:
Sting: Near-storage accelerator framework for scalable triangle counting and beyond. 171:1-171:6 - Shaoze Fan, Haoshu Lu, Shun Zhang, Ningyuan Cao, Xin Zhang, Jing Li:
Graph-Transformer-based Surrogate Model for Accelerated Converter Circuit Topology Design. 172:1-172:6 - Rupesh Raj Karn, Kashif Nawaz, Ibrahim Abe M. Elfadel:
Order-Preserving Cryptography for the Confidential Inference in Random Forests: FPGA Design and Implementation. 173:1-173:6 - Zhaole Chu, Zhou Zhang, Peiquan Jin, Xiaoliang Wang, Yongping Luo, Xujian Zhao:
LIVAK: A High-Performance In-Memory Learned Index for Variable-Length Keys. 174:1-174:6 - Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang:
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. 175:1-175:6 - Shiju Lin, Bentian Jiang, Weihua Sheng, Evangeline F. Y. Young:
Size-Optimized Depth-Constrained Large Parallel Prefix Circuits. 176:1-176:6 - Weihua Xiao, Tingting Zhang, Xingyue Qian, Jie Han, Weikang Qian:
Efficient Approximate Decomposition Solver using Ising Model. 177:1-177:6 - Yujie Zhao, Yang Katie Zhao, Cheng Wan, Yingyan Celine Lin:
3D-Carbon: An Analytical Carbon Modeling Tool for 3D and 2.5D Integrated Circuits. 178:1-178:6 - Najmeh Nazari, Chongzhou Fang, Hosein Mohammadi Makrani, Behnam Omidi, Mahdi Eslamimehr, Setareh Rafatirad, Avesta Sasan, Hossein Sayadi, Khaled N. Khasawneh, Houman Homayoun:
Architectural Whispers: Robust Machine Learning Models Fingerprinting via Frequency Throttling Side-Channels. 179:1-179:6 - Fan Zhang, Li Yang, Deliang Fan:
Hyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM/SRAM Memory. 180:1-180:6 - Han Cho, Dongjun Kim, Seungeon Hwang, Jongsun Park:
SpARC: Token Similarity-Aware Sparse Attention Transformer Accelerator via Row-wise Clustering. 181:1-181:6 - Fan Zhang, Amitesh Sridharan, Wilman Tsai, Yiran Chen, Shan X. Wang, Deliang Fan:
Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning. 182:1-182:6 - Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang:
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. 183:1-183:6 - Manaar Alam, Michail Maniatakos:
AdvHunter: Detecting Adversarial Perturbations in Black-Box Neural Networks through Hardware Performance Counters. 184:1-184:6 - Xianzhang Chen, Xingjie Zhou, Wei Li, Xi Yu, Duo Liu, Yujuan Tan, Ao Ren:
FinerDedup: Sifting Fingerprints for Efficient Data Deduplication on Mobile Devices. 185:1-185:6 - Jinkai Wang, Zekun Wang, Bojun Zhang, Zhengkun Gu, Youxiang Chen, Weisheng Zhao, Yue Zhang:
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications. 186:1-186:6 - Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu:
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. 187:1-187:6 - Yu Jin, Chunlu Wang, Pengfei Qiu, Chang Liu, Yihao Yang, Hongpei Zheng, Yongqiang Lyu, Xiaoyong Li, Gang Qu, Dongsheng Wang:
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR. 188:1-188:6 - Jonathan Hao-Cheng Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, Jeyavijayan Rajendran, Yiran Chen:
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. 189:1-189:6 - Zhiqiang Liu, Wenjian Yu:
PowerRChol: Efficient Power Grid Analysis Based on Fast Randomized Cholesky Factorization. 190:1-190:6 - Manting Zhang, Jialin Cao, Kejia Shi, Keqing Zhao, Genhao Zhang, Jun Yu, Kun Wang:
FNM-Trans: Efficient FPGA-based Transformer Architecture with Full N: M Sparsity. 191:1-191:6 - Yibo Qiao, Weiping Xie, Shunyuan Lou, Qian Jin, Lichao Zeng, Yining Chen, Qi Sun, Cheng Zhuo:
Minimizing Labeling, Maximizing Performance: A Novel Approach to Nanoscale Scanning Electron Microscope (SEM) Defect Segmentation. 192:1-192:6 - Weiliang Huang, Jinyu Bai, Wang Kang, Zhaohao Wang, Kaihua Cao, Hongxi Liu, He Zhang, Weisheng Zhao:
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency. 193:1-193:6 - Hyunsung Yoon, Jae-Joon Kim:
Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration. 194:1-194:6 - Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Dian Zhou, Xuan Zeng:
Efficient ILT via Multigrid-Schwartz Method. 195:1-195:6 - Ping Liu, Tong Zhang, Xiaoqin Feng, Yanying Ma, Fengyuan Ren:
Enabling Low Latency for ECQF based Flow Aggregation Scheduling in Time-Sensitive Networking. 196:1-196:6 - Siyuan Liang, Yushen Zhang, Rana Altay, Hudson Gasvoda, Mengchu Li, Ismail Emre Araci, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
LaMUX: Optimized Logic-Gate-Enabled High-Performance Microfluidic Multiplexer Design. 197:1-197:6 - Zifei Cai, Anaoxue Huang, Yifeng Xiong, Dejiang Mu, Xiangshui Miao, Xingsheng Wang:
Multi-order Differential Neural Network for TCAD Simulation of the Semiconductor Devices. 198:1-198:6 - Yifan Gong, Yushu Wu, Zheng Zhan, Pu Zhao, Liangkai Liu, Chao Wu, Xulong Tang, Yanzhi Wang:
LOTUS: learning-based online thermal and latency variation management for two-stage detectors on edge devices. 199:1-199:6 - Jinming Ma, Xiuhong Li, Zihan Wang, Xingcheng Zhang, Shengen Yan, Yuting Chen, Yueqian Zhang, Minxi Jin, Lijuan Jiang, Yun Liang, Chao Yang, Dahua Lin:
A Holistic Functionalization Approach to Optimizing Imperative Tensor Programs in Deep Learning. 200:1-200:6 - Wentong Li, Dingcui Yu, Yunpeng Song, Longfei Luo, Liang Shi:
ElasticZRAM: Revisiting ZRAM for Swapping on Mobile Devices. 201:1-201:6 - Haoqin Huang, Pengcheng Yao, Zhaozeng An, Yufei Sun, Ao Hu, Peng Xu, Long Zheng, Xiaofei Liao, Hai Jin:
SpaHet: A Software/Hardware Co-design for Accelerating Heterogeneous-Sparsity based Sparse Matrix Multiplication. 202:1-202:6 - Qinggang Wang, Long Zheng, Zhaozeng An, Haoqin Huang, Haoran Zhu, Yu Huang, Pengcheng Yao, Xiaofei Liao, Hai Jin:
High-Performance and Resource-Efficient Dynamic Memory Management in High-Level Synthesis. 203:1-203:6 - Jinting Wu, Haodong Zheng, Yu Wang, Tai Yue, Fengwei Zhang:
TATOO: A Flexible Hardware Platform for Binary-Only Fuzzing. 204:1-204:6 - Dajiang Liu, Decai Pan, Xiao Xiong, Jiaxing Shang, Shouyi Yin:
PMP: Pattern Morphing-based Memory Partitioning in High-Level Synthesis. 205:1-205:6 - Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu:
Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems. 206:1-206:6 - Yuhang Liu, Mingyu Chen:
Planaria: Pattern Directed Cross-page Composite Prefetcher. 207:1-207:6 - Yuheng Su, Qiusong Yang, Yiwei Ci:
Predicting Lemmas in Generalization of IC3. 208:1-208:6 - Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao:
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. 209:1-209:6 - Dong Yin, Huizhang Luo, Jeff Zhang, Mingxing Duan, Wangdong Yang, Zhuo Tang, Kenli Li:
zeroTT: A Two-Step State Transition Avoidance Scheme for MLC STT-RAM. 210:1-210:6 - Sitian Chen, Haobin Tan, Amelie Chi Zhou, Yusen Li, Pavan Balaji:
UpDLRM: Accelerating Personalized Recommendation using Real-World PIM Architecture. 211:1-211:6 - Xi Wang, Gwok-Waa Wan, Sam-Zaak Wong, Layton Zhang, Tianyang Liu, Qi Tian, Jianmin Ye:
ChatCPU: An Agile CPU Design and Verification Platform with LLM. 212:1-212:6 - Weizhi Feng, Yicheng Liu, Jiaxiang Liu, David N. Jansen, Lijun Zhang, Zhilin Wu:
Formally Verifying Arithmetic Chisel Designs for All Bit Widths at Once. 213:1-213:6 - Zheng Xu, Xu Dai, Shaojun Wei, Shouyi Yin, Yang Hu:
GSPO: A Graph Substitution and Parallelization Joint Optimization Framework for DNN Inference. 214:1-214:6 - Jeonghwan Kang, Jaeyeol Park, Jiwon Seo, Donghyun Kwon:
Look Before You Access: Efficient Heap Memory Safety for Embedded Systems on ARMv8-M. 215:1-215:6 - Weiguang Pang, Xu Jiang, Songran Liu, Lei Qiao, Kexue Fu, Longxiang Gao, Wang Yi:
Control Flow Divergence Optimization by Exploiting Tensor Cores. 216:1-216:6 - Bu Chen, Zhangcheng Huang, Qi Zheng, Weiyi Tang, Jingyi Wang, Hankun Lv, Chixiao Chen, Jianlu Wang, Qi Liu:
CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. 217:1-217:6 - Liang-Ting Chen, Hung-Ru Kuo, Yih-Lang Li, Mango C.-T. Chao:
Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search. 218:1-218:6 - Rongliang Fu, Robert Wille, Tsung-Yi Ho:
RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming. 219:1-219:6 - Pingcheng Dong, Yonghao Tan, Dong Zhang, Tianwei Ni, Xuejiao Liu, Yu Liu, Peng Luo, Luhong Liang, Shih-Yang Liu, Xijie Huang, Huaiyu Zhu, Yun Pan, Fengwei An, Kwang-Ting Cheng:
Genetic Quantization-Aware Approximation for Non-Linear Operations in Transformers. 220:1-220:6 - Taehyun Kim, Kwanseok Choi, Youngmock Cho, Jaehoon Cho, Hyuk-Jae Lee, Jaewoong Sim:
MoNDE: Mixture of Near-Data Experts for Large-Scale Sparse Models. 221:1-221:6 - Nandish Chattopadhyay, Amira Guesmi, Muhammad Abdullah Hanif, Bassem Ouni, Muhammad Shafique:
Defending against Adversarial Patches using Dimensionality Reduction. 222:1-222:6 - Jiaming Liu, Zihao Liu, Xuan Huang, Ruoxi Zhu, Qi Zheng, Zhijian Hao, Tao Liu, Jun Tao, Yibo Fan:
Auto-ISP: An Efficient Real-Time Automatic Hyperparameter Optimization Framework for ISP Hardware System. 223:1-223:6 - Haochuan Wan, Linjie Ma, Antong Li, Pingqiang Zhou, Jingyi Yu, Xin Lou:
ZeroTetris: A Spacial Feature Similarity-based Sparse MLP Engine for Neural Volume Rendering. 224:1-224:6 - Junyoung Park, Myeonggu Kang, Yunki Han, Yanggon Kim, Jaekang Shin, Lee-Sup Kim:
Token-Picker: Accelerating Attention in Text Generation with Minimized Memory Transfer via Probability Estimation. 225:1-225:6 - Yu Qian, Kai Ni, Thomas Kämpfe, Cheng Zhuo, Xunzhao Yin:
C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium. 226:1-226:6 - Dongjin Shin, Insu Choi, Joon-Sung Yang:
ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm. 227:1-227:6 - Jiawei Geng, Zongwei Zhu, Weihong Liu, Xuehai Zhou, Boyu Li:
PowerLens: An Adaptive DVFS Framework for Optimizing Energy Efficiency in Deep Neural Networks. 228:1-228:6 - Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu:
WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. 229:1-229:6 - Xiaolong Yang, Yang Wang, Yubin Qin, Jiachen Wang, Shaojun Wei, Yang Hu, Shouyi Yin:
FQP: A Fibonacci Quantization Processor with Multiplication-Free Computing and Topological-Order Routing. 230:1-230:6 - Zhenxing Dou, Ming Cheng, Ming Jia, Peng Wang:
BNN-YEO: an efficient Bayesian Neural Network for yield estimation and optimization. 231:1-231:6 - Lei Xu, Zhiwen Mo, Qin Wang, Jianfei Jiang, Naifeng Jing:
Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. 232:1-232:6 - Tianchen Gu, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng:
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. 233:1-233:6 - Zhisheng Zeng, Jikang Liu, Zhipeng Huang, Ye Cai, Biwei Xie, Yungang Bao, Xingquan Li:
Net Resource Allocation: A Desirable Initial Routing Step. 234:1-234:6 - Alessio Mascolini, Sebastiano Gaiardelli, Francesco Ponzio, Nicola Dall'Ora, Enrico Macii, Sara Vinco, Santa Di Cataldo, Franco Fummi:
VARADE: a Variational-based AutoRegressive model for Anomaly Detection on the Edge. 235:1-235:6 - Francesco Giulio Blanco, Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
A Deep Reinforcement Learning based Online Scheduling Policy for Deep Neural Network Multi-Tenant Multi-Accelerator Systems. 236:1-236:6 - Doyun Kim, Jaemin Park, Youngmin Oh, Bosun Hwang:
TraceFormer: S-parameter Prediction Framework for PCB Traces based on Graph Transformer. 237:1-237:6 - Fengkun Dong, Guoqing Xiao, Haotian Wang, Yikun Hu, Kenli Li, Wangdong Yang:
TAPMM: A Traffic-Aware Page Mapping Method for Multi-level NUMA Systems. 238:1-238:6 - Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu:
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. 239:1-239:6 - Rassul Bairamkulov, Mingfei Yu, Giovanni De Micheli:
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits. 240:1-240:6 - Yu Qian, Zeyu Yang, Kai Ni, Alptekin Vardar, Thomas Kämpfe, Xunzhao Yin:
HyCiM: A Hybrid Computing-in-Memory QUBO Solver for General Combinatorial Optimization Problems with Inequality Constraints. 241:1-241:6 - Takefumi Koike, Hiromitsu Awano, Takashi Sato:
Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval. 242:1-242:6 - Yibo Du, Ying Wang, Bing Li, Fuping Li, Shengwen Liang, Huawei Li, Xiaowei Li, Yinhe Han:
Chiplever: Towards Effortless Extension of Chiplet-based System for FHE. 243:1-243:6 - Weiguo Li, Zhipeng Huang, Bei Yu, Wenxing Zhu, Xingquan Li:
Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree. 244:1-244:6 - Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang:
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. 245:1-245:6 - Chao Li, Zhicheng Xu, Bo Wen, Ruibin Mao, Can Li, Thomas Kämpfe, Kai Ni, Xunzhao Yin:
FeBiM: Efficient and Compact Bayesian Inference Engine Empowered with Ferroelectric In-Memory Computing. 246:1-246:6 - Shamik Kundu, Mirazul Haque, Sanjay Das, Wei Yang, Kanad Basu:
MENDNet: Just-in-time Fault Detection and Mitigation in AI Systems with Uncertainty Quantification and Multi-Exit Networks. 247:1-247:6 - Xuanda Lin, Huinan Tian, Wenxiao Xue, Lanqi Ma, Jialin Cao, Manting Zhang, Jun Yu, Kun Wang:
FLAME: Fully Leveraging MoE Sparsity for Transformer on FPGA. 248:1-248:6 - Zhiyuan Chen, Kun Yang, Kui Ren:
CDS: An Anti-Aging Calibratable Digital Sensor for Detecting Multiple Types of Fault Injection Attacks. 249:1-249:6 - Chen Chen, Yuhang Huang, Shuiguang Deng, Jianwei Yin, Xinkui Zhao:
Sharry: An Efficient and Sharing Far Memory System. 250:1-250:6 - Paul Scheffler, Luca Colagrande, Luca Benini:
SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. 251:1-251:6 - Hao-Hsiang Hsiao, Pruek Vanna-Iampikul, Yi-Chen Lu, Sung Kyu Lim:
ML-based Physical Design Parameter Optimization for 3D ICs: From Parameter Selection to Optimization. 252:1-252:6 - Shiyu Guo, Yuhao Ju, Xi Chen, Jie Gu:
LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices. 253:1-253:6 - Li Ni, Jiliang Zhang:
S2RAM PUF: An Ultra-low Power Subthreshold SRAM PUF with Zero Bit Error Rate. 254:1-254:6 - Haifeng Liu, Long Zheng, Yu Huang, Haoyan Huang, Xiaofei Liao, Hai Jin:
Towards Redundancy-Free Recommendation Model Training via Reusable-aware Near-Memory Processing. 255:1-255:6 - Yanjie Tan, Yifu Zhu, Zhaoyang Huang, Feiteng Nie, Huailiang Tan:
A HW/SW Co-Design of Video Dehazing Accelerator Using Decoupled Local Atmospheric Light Prior. 256:1-256:6 - Xidi Ma, Weichen Zhang, Xueyan Wang, Tianyang Yu, Bi Wu, Gang Qu, Weisheng Zhao:
A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration. 257:1-257:6 - Yufeng Li, Qiusong Yang, Yiwei Ci, Enyuan Tian:
SEPE-SQED: Symbolic Quick Error Detection by Semantically Equivalent Program Execution. 258:1-258:6 - Jahyun Koo, Dahoon Park, Sangwoo Jung, Jaeha Kung:
OPAL: Outlier-Preserved Microscaling Quantization Accelerator for Generative Large Language Models. 259:1-259:6 - Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi:
Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning. 260:1-260:6 - Luigi Capogrosso, Enrico Fraccaroli, Samarjit Chakraborty, Franco Fummi, Marco Cristani:
MTL-Split: Multi-Task Learning for Edge Devices using Split Computing. 261:1-261:6 - Jialong Liu, Wenjun Tang, Deyun Chen, Chen Jiang, Huazhong Yang, Xueqing Li:
Cross-Layer Exploration and Chip Demonstration of In-Sensor Computing for Large-Area Applications with Differential-Frame ROM-Based Compute-In-Memory. 262:1-262:6 - Yueyin Bai, Keqing Zhao, Yang Liu, Hongji Wang, Hao Zhou, Xiaoxing Wu, Jun Yu, Kun Wang:
CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. 263:1-263:6 - Mingyue Wang, Yuanqing Cheng, Yage Lin, Kelin Peng, Shunchuan Yang, Zhou Jin, Wei W. Xing:
MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction. 264:1-264:6 - Feiwen Zhu, Arkadiusz Nowaczynski, Rundong Li, Jie Xin, Yifei Song, Michal Marcinkiewicz, Sukru Burc Eryilmaz, Jun Yang, Michael Andersch:
ScaleFold: Reducing AlphaFold Initial Training Time to 10 Hours. 265:1-265:6 - Liukai Xu, Shuai Yuan, Dengfeng Wang, Yiming Chen, Xueqing Li, Yanan Sun:
HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration. 266:1-266:6 - Ludwig Schmid, Sunghye Park, Robert Wille:
Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers. 267:1-267:6 - Ahmed F. AbouElhamayed, Susanne Balle, Deshanand P. Singh, Mohamed S. Abdelfattah:
Beyond Inference: Performance Analysis of DNN Server Overheads for Computer Vision. 268:1-268:6 - Mingjia Fan, Xiaoming Chen, Dechuang Yang, Zhou Jin, Weifeng Liu:
ReCG: ReRAM-Accelerated Sparse Conjugate Gradient. 269:1-269:6 - Wilfread Guillemé, Angeliki Kritikakou, Youri Helen, Cédric Killian, Daniel Chillet:
HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks. 270:1-270:6 - Haodong Lu, Zhiyuan Ma, Xinran Li, Shiyan Bi, Xiaoming He, Kun Wang:
TrafficHD: Efficient Hyperdimensional Computing for Real-Time Network Traffic Analytics. 271:1-271:6 - Xinkuang Geng, Siting Liu, Leibo Liu, Jie Han, Honglan Jiang:
QUQ: Quadruplet Uniform Quantization for Efficient Vision Transformer Inference. 272:1-272:6 - Yuntao Wei, Xueyan Wang, Song Bian, Yicheng Huang, Weisheng Zhao, Yier Jin:
PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator. 273:1-273:6 - Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng:
VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. 274:1-274:6 - Brendan Reidy, Sepehr Tabrizchi, Mohammadreza Mohammadi, Shaahin Angizi, Arman Roohi, Ramtin Zand:
HiRISE: High-Resolution Image Scaling for Edge ML via In-Sensor Compression and Selective ROI. 275:1-275:6 - Ali Aghdaei, Zhuo Feng:
inGRASS: Incremental Graph Spectral Sparsification via Low-Resistance-Diameter Decomposition. 276:1-276:6 - John Anticev, Ali Aghdaei, Wuxinlin Cheng, Zhuo Feng:
SGM-PINN: Sampling Graphical Models for Faster Training of Physics-Informed Neural Networks. 277:1-277:6 - Niklas Jungnitz, Oliver Keszöcze:
SAS - A Framework for Symmetry-based Approximate Synthesis. 278:1-278:6 - Zhengqi Gao, Dinghuai Zhang, Luca Daniel, Duane S. Boning:
NOFIS: Normalizing Flow for Rare Circuit Failure Analysis. 279:1-279:6 - Yinuo Bai, Enxin Yi, Wei W. Xing, Bei Yu, Zhou Jin:
Unleashing the Potential of AQFP Logic Placement via Entanglement Entropy and Projection. 280:1-280:6 - Xingchen Li, Zhe Zhou, Qilin Zheng, Guangyu Sun, Qiankun Wang, Chenhao Xue:
A Software-Hardware Co-design Solution for 3D Inner Structure Reconstruction. 281:1-281:6 - Nimish Mishra, Rahul Arvind Mool, Anirban Chakraborty, Debdeep Mukhopadhyay:
Plug Your Volt: Protecting Intel Processors against Dynamic Voltage Frequency Scaling based Fault Attacks. 282:1-282:6 - Xia Zeng, Banglong Liu, Zhenbing Zeng, Zhiming Liu, Zhengfeng Yang:
Safe Controller Synthesis for Nonlinear Systems via Reinforcement Learning and PAC Approximation. 283:1-283:6 - Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. 284:1-284:6 - Shipei Qu, Xiaolin Zhang, Chi Zhang, Dawu Gu:
Trapped by Your WORDs: (Ab)using Processor Exception for Generic Binary Instrumentation on Bare-metal Embedded Devices. 285:1-285:6 - You Li, Guannan Zhao, Yunqi He, Hai Zhou:
Evaluating the Security of Logic Locking on Deep Neural Networks. 286:1-286:6 - Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim:
GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. 287:1-287:6 - Xinyu Sun, Yu Zhang, Shuo Liu, Yi Zhai:
Crop: An Analytical Cost Model for Cross-Platform Performance Prediction of Tensor Programs. 288:1-288:6 - Chenxi Li, Boyuan Zhang, Yongqiang Duan, Yang Li, Zuochang Ye, Weifeng Liu, Dingwen Tao, Zhou Jin:
MASC: A Memory-Efficient Adjoint Sensitivity Analysis through Compression Using Novel Spatiotemporal Prediction. 289:1-289:6 - Zeyu Yang, Qingrong Huang, Yu Qian, Kai Ni, Thomas Kämpfe, Xunzhao Yin:
Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability. 290:1-290:6 - Lucas Roquet, Fernando Fernandes dos Santos, Paolo Rech, Marcello Traiola, Olivier Sentieys, Angeliki Kritikakou:
Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models. 291:1-291:6 - Johannes Müller, Anna Lena Duque Antón, Lucas Deutschmann, Dino Mehmedagic, Cristiano Rodrigues, Daniel Oliveira, Mohammad Rahmani Fadiheh, Keerthikumara Devarajegowda, Sandro Pinto, Dominik Stoffel, Wolfgang Kunz:
MCU-Wide Timing Side Channels and Their Detection. 292:1-292:6 - Hamid Farzaneh, João Paulo C. de Lima, Ali Nezhadi Khelejani, Asif Ali Khan, Mahta Mayahinia, Mehdi B. Tahoori, Jerónimo Castrillón:
SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs. 293:1-293:6 - Mohamadreza Rostami, Shaza Zeitouni, Rahul Kande, Chen Chen, Pouya Mahmoody, Jeyavijayan Rajendran, Ahmad-Reza Sadeghi:
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection. 294:1-294:6 - Mohsen Ahmadzadeh, Georges G. E. Gielen:
Using Probabilistic Model Rollouts to Boost the Sample Efficiency of Reinforcement Learning for Automated Analog Circuit Sizing. 295:1-295:6 - Wenxing Li, Hongqin Lyu, Shengwen Liang, Tiancheng Wang, Huawei Li:
SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning. 296:1-296:6 - Shengyi Ji, Chubo Liu, Yan Ding, Qing Liao, Zhuo Tang:
A Real-time Execution System of Multimodal Transformer through PIM-GPU Collaboration. 297:1-297:6 - Giacomo Lancellotti, Simone Perriello, Alessandro Barenghi, Gerardo Pelosi:
Design of a Quantum Walk Circuit to Solve the Subset-Sum Problem. 298:1-298:6 - Galib Ibne Haidar, Kimia Zamiri Azar, Hadi Mardani Kamali, Mark M. Tehranipoor, Farimah Farahmandi:
GATE-SiP: Enabling Authenticated Encryption Testing in Systems-in-Package. 299:1-299:6 - Meixun Qu, Jie He, Zlatan Tucakovic, Ezio Bartocci, Dejan Nickovic, Haris Isakovic, Radu Grosu:
DeepRIoT: Continuous Integration and Deployment of Robotic-IoT Applications. 300:1-300:6 - Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk:
Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. 301:1-301:6 - Jialin Song, Aidan M. Swope, Robert Kirby, Rajarshi Roy, Saad Godil, Jonathan Raiman, Bryan Catanzaro:
CircuitVAE: Efficient and Scalable Latent Circuit Optimization. 302:1-302:6 - Wei Li, Rongjian Liang, Anthony Agnesina, Haoyu Yang, Chia-Tung Ho, Anand Rajaram, Haoxing Ren:
DGR: Differentiable Global Router. 303:1-303:6 - Fangzhou Ye, Lingxiang Yin, Amir Ghazizadeh Ahsaei, Hao Zheng:
EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization. 304:1-304:6 - Nikhil Chawla, Chen Liu, Abhishek Chakraborty, Igor Chervatyuk, Thais Moreira Hamasaki, Ke Sun, Henrique Kawakami:
Uncovering Software-Based Power Side-Channel Attacks on Apple M1/M2 Systems. 305:1-305:6 - Hanrui Wang, Daniel Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han:
Q-Pilot: Field Programmable Qubit Array Compilation with Flying Ancillas. 306:1-306:6 - Boyang Cheng, Jianbo Liu, Steven Davis, Zephan M. Enciso, Yiyang Zhang, Ningyuan Cao:
VAE-HDC: Efficient and Secure Hyper-dimensional Encoder Leveraging Variation Analog Entropy. 307:1-307:6 - Yuxuan Yin, Rebecca Chen, Chen He, Peng Li:
Data-Efficient Conformalized Interval Prediction of Minimum Operating Voltage Capturing Process Variations. 308:1-308:6 - Aggelos Ferikoglou, Andreas Kosmas Kakolyris, Vasilis Kypriotis, Dimosthenis Masouros, Dimitrios Soudris, Sotirios Xydis:
Data-driven HLS optimization for reconfigurable accelerators. 309:1-309:6 - Ziyu Liu, Tong Zhou, Yukui Luo, Xiaolin Xu:
TBNet: A Neural Architectural Defense Framework Facilitating DNN Model Protection in Trusted Execution Environments. 310:1-310:6 - Yunxiang Zhang, Omar Al Kailani, Wenfeng Zhao:
AdderNet 2.0: Optimal FPGA Acceleration of AdderNet with Activation-Oriented Quantization and Fused Bias Removal based Memory Optimization. 311:1-311:6 - Mahya Saffarpour, Weitai Qian, Kourosh Vali, Begum Kasap, Herman L. Hedriana, Soheil Ghiasi:
Deep Harmonic Finesse: Signal Separation in Wearable Systems with Limited Data. 312:1-312:6 - Qilin Zheng, Ziru Li, Jonathan Ku, Yitu Wang, Brady Taylor, Deliang Fan, Yiran Chen:
Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference. 313:1-313:6 - Zhangying He, Houman Homayoun, Hossein Sayadi:
Beyond Conventional Defenses: Proactive and Adversarial-Resilient Hardware Malware Detection using Deep Reinforcement Learning. 314:1-314:6 - Sumit Kumar Jha, Susmit Jha, Rickard Ewetz, Alvaro Velasquez:
On the Design of Novel Attention Mechanism for Enhanced Efficiency of Transformers. 315:1-315:6 - Keming Fan, Wei-Chen Chen, Sumukh Pinge, H.-S. Philip Wong, Tajana Rosing:
Efficient Open Modification Spectral Library Searching in High-Dimensional Space with Multi-Level-Cell Memory. 316:1-316:6 - Wei-Chen Chen, H.-S. Philip Wong, Sara Achour:
Bitwise Adaptive Early Termination in Hyperdimensional Computing Inference. 317:1-317:6 - Zihu Wang, Karthik Somayaji N. S., Peng Li:
Learn-by-Compare: Analog Performance Prediction using Contrastive Regression with Design Knowledge. 318:1-318:6 - Gianfranco Ciardo, Andrew S. Miner, Lichuan Deng, Junaid Babar:
RexBDDs: Reduction-on-Edge Complement-and-Swap Binary Decision Diagrams. 319:1-319:6 - Chetan Choppali Sudarshan, Aman Arora, Vidya A. Chhabria:
GreenFPGA: Evaluating FPGAs as Environmentally Sustainable Computing Solutions. 320:1-320:6 - Siyuan Niu, Akel Hashim, Costin Iancu, Wibe Albert de Jong, Ed Younis:
Effective Quantum Resource Optimization via Circuit Resizing in BQSKit. 321:1-321:6 - Junhuan Yang, Hanchen Wang, Yi Sheng, Youzuo Lin, Lei Yang:
EdGeo: A Physics-guided Generative AI Toolkit for Geophysical Monitoring on Edge Devices. 322:1-322:6 - Heiko Mantel, Joachim Schmidt, Thomas Schneider, Maximilian Stillger, Tim Weißmantel, Hossein Yalame:
HyCaMi: High-Level Synthesis for Cache Side-Channel Mitigation. 323:1-323:6 - Yingnan Zhao, Ke Wang, Jiaqi Yang, Ahmed Louri:
An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference. 324:1-324:6 - Zewei Mo, Yingheng Li, Aditya Pawar, Xulong Tang, Jun Yang, Youtao Zhang:
FCM: A Fusion-aware Wire Cutting Approach for Measurement-based Quantum Computing. 325:1-325:6 - Akshat Ramachandran, Zishen Wan, Geonhwa Jeong, John Gustafson, Tushar Krishna:
Algorithm-Hardware Co-Design of Distribution-Aware Logarithmic-Posit Encodings for Efficient DNN Inference. 326:1-326:6 - Zhongzhi Yu, Zheng Wang, Yuhan Li, Ruijie Gao, Xiaoya Zhou, Sreenidhi Reddy Bommu, Yang Katie Zhao, Yingyan (Celine) Lin:
EDGE-LLM: Enabling Efficient Large Language Model Adaptation on Edge Devices via Unified Compression and Adaptive Layer Voting. 327:1-327:6 - Daniel Xing, Ankur Srivastava:
A High Level Approach to Co-Designing 3D ICs. 328:1-328:6 - Hao Cheng, Georgios Fotiadis, Johann Großschädl, Daniel Page, Thinh Hung Pham, Peter Y. A. Ryan:
RISC-V Instruction Set Extensions for Multi-Precision Integer Arithmetic: A Case Study on Post-Quantum Key Exchange Using CSIDH-512. 329:1-329:6 - Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Kyungjun Min, Seonghyeon Park, Bodhisatta Pramanik:
PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. 330:1-330:6 - Saeed Seyedfaraji, Severin Jager, Salar Shakibhamedan, Asad Aftab, Semeen Rehman:
OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-offs. 331:1-331:6 - Donghyeok Heo, Hyeonsu Bang, Jong Hwan Ko:
TraiNDSim: A Simulation Framework for Comprehensive Performance Evaluation of Neuromorphic Devices for On-Chip Training. 332:1-332:6 - Binqi Sun, Tomasz Kloda, Chu-Ge Wu, Marco Caccamo:
Partitioned Scheduling and Parallelism Assignment for Real-Time DNN Inference Tasks on Multi-TPU. 333:1-333:6 - Miaomiao Jiang, Yilan Zhu, Honghui You, Cheng Tan, Zhaoying Li, Jiming Xu, Lei Ju:
FHE-CGRA: Enable Efficient Acceleration of Fully Homomorphic Encryption on CGRAs. 334:1-334:6 - Munhyeon Kim, Jae-Joon Kim:
4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors. 335:1-335:6 - Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan:
Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. 336:1-336:6 - Quan Cheng, Qiufeng Li, Longyang Lin, Wang Liao, Liuyao Dai, Hao Yu, Masanori Hashimoto:
How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -. 337:1-337:6 - Chiara Bozzini, Michele Boldo, Enrico Martini, Nicola Bombieri:
Late Breaking Results: A real-time diffusion-based filter for human pose estimation on edge devices. 338:1-338:2 - Tianliang Ma, Guangxi Fan, Xuguang Sun, Zhihui Deng, Kain Lu Low, Leilai Shao:
Late Breaking Results: Fast System Technology Co-Optimization Framework for Emerging Technology Based on Graph Neural Networks. 339:1-339:2 - Mengchu Li, Hanchen Gu, Yushen Zhang, Siyuan Liang, Hudson Gasvoda, Rana Altay, Ismail Emre Araci, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann:
Late Breaking Results: Efficient Built-in Self-Test for Microfluidic Large-Scale Integration (mLSI). 340:1-340:2 - Sercan Aygun, Mehran Shoushtari Moghadam, M. Hassan Najafi:
Late Breaking Results: TriSC: Low-Cost Design of Trigonometric Functions with Quasi Stochastic Computing. 341:1-341:2 - Simon Toni Hofmann, Marcel Walter, Robert Wille:
Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies. 342:1-342:2 - Zhenxiao Fu, Fan Chen:
Late Breaking Results: Extracting QNNs from NISQ Computers via Ensemble Learning. 343:1-343:2 - Debnath Maiti, Sumukh Prashant Bhanushali, Arindam Sanyal:
Late Breaking Results: Machine Learning Based Reference Ripple Error Suppression in Successive Approximation Register Analog-to-Digital Converters. 344:1-344:2 - Wei-Che Tseng, Zong-Ying Cai, Yi-Ping Huang, Yu-Hsiang Lo, Yao-Wen Chang:
Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards. 345:1-345:2 - Chien-Hao Tsou, Sheng-Yah Lin, Wei-Chen Hung, Yao-Wen Chang:
Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints. 346:1-346:2 - Jinhai Hu, Zhongyi Zhang, Cong Sheng Leow, Wang Ling Goh, Yuan Gao:
Late Breaking Results: Circuit-Algorithm Co-design for Learnable Audio Analog Front-End. 347:1-347:2 - Hao Gu, Jian Gu, Keyu Peng, Jun Yang, Ziran Zhu:
Late Breaking Results: Routability-Driven FPGA Macro Placement Considering Complex Cascade Shape and Region Constraints. 348:1-348:2 - Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler:
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. 349:1-349:2 - Benchao Zhu, Zheng Zeng, Jianli Chen:
Late Breaking Results: Mixed-Cell-Height Detailed Placement under Multi-Cell Spacing Constraints. 350:1-350:2 - Dimosthenis Masouros, Aggelos Ferikoglou, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris:
Late Breaking Results: Language-level QoR modeling for High-Level Synthesis. 351:1-351:2 - Jihai Meng, Shaohong Weng, Zhijie Cai, Yilu Chen, Zhifeng Lin, Jianli Chen:
Late Breaking Results: Coulomb Force-Based Routability-Driven Placement Considering Global and Local Congestion. 352:1-352:2 - Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli:
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration. 353:1-353:2 - Zhengang Li, Xuan Shen, Geng Yuan, Masoud Zabihi, Tomoharu Yamauchi, Yanzhi Wang, Olivia Chen:
Late Breaking Result: AQFP-aware Binary Neural Network Architecture Search. 354:1-354:2 - Yinghua Hu, Hari Cherupalli, Mike Borza, Deepak D. Sherlekar:
Late Breaking Results: On the One-Key Premise of Logic Locking. 355:1-355:2 - Arash Ardakani, Minwoo Kang, Kevin He, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek:
Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas. 356:1-356:2 - Filippo Ziche, Nicola Bombieri:
Late Breaking Results: Evaluation of Human Action Quality with Linear Recurrent Units and Graph Attention Networks on Embedded Systems. 357:1-357:2 - Xabier Iturbe, Bernabé Linares-Barranco, Sio-Hoi Ieng, Arne Erdmann, Luca Peres, Oliver Rhodes, Rafael Tornero, Manolis Sifalakis, Marcel D. van de Burgwal, Amirreza Yousefzadeh, Maha Kooli, Riccardo Alidori, Pavel Zaykov:
Invited: Neuromorphic Vision Modalities in the NimbleAI 3D Chip. 358:1-358:4 - Matej Hejda, Federico Marchesin, George Papadimitriou, Dimitris Gizopoulos, Benoît Charbonnier, Régis Orobtchouk, Peter Bienstman, Thomas Van Vaerenbergh, Fabio Pavanello:
Invited: Neuromorphic Architectures Based on Augmented Silicon Photonics Platforms. 359:1-359:4 - Xiangyu Ren, Tianyu Zhang, Xiong Xu, Yicong Zheng, Shengyu Zhang:
Invited: Leveraging Machine Learning for Quantum Compilation Optimization. 360:1-360:4 - Zhiding Liang, Gang Liu, Zheyuan Liu, Jinglei Cheng, Tianyi Hao, Kecheng Liu, Hang Ren, Zhixin Song, Ji Liu, Fanny Ye, Yiyu Shi:
Invited: Graph Learning for Parameter Prediction of Quantum Approximate Optimization Algorithm. 361:1-361:4 - Zichang He, Shouvanik Chakrabarti, Dylan Herman, Niraj Kumar, Changhao Li, Pierre Minssen, Pradeep Niroula, Ruslan Shaydulin, Yue Sun, Shree Hari Sureshbabu, Romina Yalovetzky, Marco Pistoia:
Invited: Challenges and Opportunities of Quantum Optimization in Finance. 362:1-362:4 - Alex Christopher Stutts, Divake Kumar, Theja Tulabandhula, Amit Ranjan Trivedi:
Invited: Conformal Inference meets Evidential Learning: Distribution-Free Uncertainty Quantification with Epistemic and Aleatoric Separability. 363:1-363:4 - Shreyas Sen, Arunashish Datta:
Invited: Human-Inspired Distributed Wearable AI. 364:1-364:4 - Lingyi Huang, Cheng Yang, Yu Gong, Yang Sui, Xiao Zang, Anthony Goeckner, Qi Zhu, Bo Yuan:
Invited: Algorithm and Hardware Co-Design for Energy-Efficient Neural SLAM. 365:1-365:4 - Semanti Basu, Semir Tatlidil, Moon Hwan Kim, Steven A. Sloman, R. Iris Bahar:
Invited: Using Causal Information to Enable More Efficient Robot Operation. 366:1-366:4 - Sabrina M. Neuman, Brian Plancher, Vijay Janapa Reddi:
Invited: The Magnificent Seven Challenges and Opportunities in Domain-Specific Accelerator Design for Autonomous Systems. 367:1-367:4 - Yuanfan Xu, Jincheng Yu, Suquan Zhang, Yunfei Xiang, Hongyang Jia, Yu Wang:
Invited: Automatic Hardware/Software Design for High-Speed Autonomous Unmanned Aerial Vehicles Guided by a Flight Model. 368:1-368:4 - Yingbing Huang, Lily Jiaxin Wan, Hanchen Ye, Manvi Jha, Jinghua Wang, Yuhong Li, Xiaofan Zhang, Deming Chen:
Invited: New Solutions on LLM Acceleration, Optimization, and Application. 369:1-369:4 - Manil Dev Gomony, Bas Ahn, Rick Luiken, Yashvardhan Biyani, Anteneh Gebregiorgis, Axel Laborieux, Friedemann Zenke, Said Hamdioui, Henk Corporaal:
Invited: Achieving PetaOps/W Edge-AI Processing. 370:1-370:4
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